Chopper stabilized bias unit element with binary weighted charge transfer capacitors
AssigneeCeremorphic, Inc.
InventorsMartin Kraemer, Ryan Boesch, Wei Xiong
Life of this patent
Estimating the term…
Abstract
A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.
Claims21
A chopper stabilized Bias Unit Element (UE) receiving a chop clock, an E digital input, and an enable bit exclusive ORed with the chop clock to generate a chopped enable bit and generating charge coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line, the Bias UE comprising:
- a plurality of logic gates, each logic gate having an input coupled to an E digital input bit and the chopped enable bit and generating a positive output and a negative output;
- the positive output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line, the negative output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line;
- each binary weighted charge transfer capacitor having an associated binary weight, the binary weight for each charge transfer capacitor including at least relative weights of 1, 2, 4, 8, and 16.
A Bias Unit Element (UE) receiving a digital E input, a chop clock, a sign bit, and transferring a bias value to a differential charge transfer bus, the Bias UE comprising:
- a chopped sign bit configured from an exclusive OR of the chop clock and the sign bit;
- a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
- a positive bias UE enabled when the chopped sign bit is positive, the positive bias UE comprising a plurality of logic gates generating a positive output and a negative output from each E input bit, each positive output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line, and each negative output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line;
- a negative bias UE enabled when the chopped sign bit is negative, the negative bias UE comprising a plurality of logic gates generating a positive output and a negative output from each E input bit, each positive output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line, and each negative output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line.
A Bias UE receiving a digital bias value E, a clear input, a chop clock and a sign input exclusive ORed to form a chopped sign bit, the Bias UE generating a bias charge coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line in response to the digital bias value E, the Bias UE comprising:
- a positive Bias UE enabled when the chopped sign bit is positive;
- a negative Bias UE enabled when the chopped sign bit is negative;
- the positive bias UE further comprising a plurality of logic gates, each logic gate coupled to one of the digital bias E bits, the chopped sign bit, and the clear bit, each logic gate generating a positive output and a negative output which is the complement of the positive output, each positive output of each of the plurality of logic gates coupled through a binary weighted charge transfer capacitor to the negative charge transfer line and each negative output of each of the plurality of logic gates coupled through a binary weighted charge transfer capacitor to the positive charge transfer line;
- the negative bias UE further comprising a plurality of logic gates, each logic gate coupled to one of the digital bias E bits, the chopped sign bit, and the clear bit, each logic gate generating a positive output and a negative output which is the complement of the positive output, each positive output of each of the plurality of logic gates coupled through a binary weighted charge transfer capacitor to the positive charge transfer line and the negative output of each of the plurality of logic gates coupled through a binary weighted charge transfer capacitor to the negative charge transfer line.
Dependencies are inferred from the claim text.