Chopper Stabilized Bias Unit Element with Binary Weighted Charge Transfer Capacitors

A Bias Unit Element (UE) receiving a digital E input, a chop clock, a sign bit, and transferring a bias value to a differential charge transfer bus, the Bias UE comprising:

• a chopped sign bit configured from an exclusive OR of the chop clock and the sign bit;
• a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
• a positive bias UE enabled when the chopped sign bit is positive, the positive bias UE comprising a plurality of logic gates generating a positive output and a negative output from each E input bit, each positive output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line, and each negative output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line;
• a negative bias UE enabled when the chopped sign bit is negative, the negative bias UE comprising a plurality of logic gates generating a positive output and a negative output from each E input bit, each positive output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line, and each negative output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line.

A Bias UE receiving a digital bias value E, a clear input, a chop clock and a sign input exclusive ORed to form a chopped sign bit, the Bias UE generating a bias charge coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line in response to the digital bias value E, the Bias UE comprising:

• a positive Bias UE enabled when the chopped sign bit is positive;
• a negative Bias UE enabled when the chopped sign bit is negative;
• the positive bias UE further comprising a plurality of logic gates, each logic gate coupled to one of the digital bias E bits, the chopped sign bit, and the clear bit, each logic gate generating a positive output and a negative output which is the complement of the positive output, each positive output of each of the plurality of logic gates coupled through a binary weighted charge transfer capacitor to the negative charge transfer line and each negative output of each of the plurality of logic gates coupled through a binary weighted charge transfer capacitor to the positive charge transfer line;
• the negative bias UE further comprising a plurality of logic gates, each logic gate coupled to one of the digital bias E bits, the chopped sign bit, and the clear bit, each logic gate generating a positive output and a negative output which is the complement of the positive output, each positive output of each of the plurality of logic gates coupled through a binary weighted charge transfer capacitor to the positive charge transfer line and the negative output of each of the plurality of logic gates coupled through a binary weighted charge transfer capacitor to the negative charge transfer line.