Back to results
US 9,524,270 B2Granted
Operand-optimized asynchronous floating-point units and method of use thereof
AssigneeCornell University
InventorsRajit Manohar, Basit R. Sheikh
Life of this patent
Estimating the term…
Abstract
Asynchronous arithmetic units including an asynchronous IEEE 754 compliant floating-point adder and an asynchronous floating point multiplier component. Arithmetic units optimized for lower power consumption and methods for optimization are disclosed.
Claims17
An asynchronous floating-point adder comprising:
- a front end component receiving a first input and second input, the first and second input being described in exponent/significand form;
- said front end analyzing the first and second input and obtaining a difference between an exponent of the first input and an exponent of the second input;
- said difference comprising a difference in exponents;
- an alignment shift component receiving the difference in exponents;
- the alignment shift component aligning significands of the first and second inputs when exponents are different;
- aligned significands being adder inputs;
- an adder component receiving the adder inputs from said alignment shift component;
- a leading one predictor (LOP)/decoder component receiving adder inputs from said alignment shift component;
- a left shift/exponent adjustment determination component receiving an output of said adder component and an output of said leading one predictor/decoder component;
- a right shift/exponent adjustment determination component receiving an output of said adder component;
- and
- a left-right selection component;
- an output of said left-right selection component being utilized to provide an output of the asynchronous floating-point adder;
- said front end component, said shifter component, said adder component, said leading one predictor (LOP)/decoder component, said left shift/exponent adjustment determination component, said right shift/exponent adjustment determination component and said left-right selection component utilizing quasi-delay insensitive (QDI) asynchronous circuits;
- said front end component, said alignment shift component, said adder component, said leading one predictor (LOP)/decoder component, said left shift/exponent adjustment determination component, said right shift/exponent adjustment determination component and said left-right selection component being asynchronously pipelined;
- asynchronously pipelining enabling optimization of operand.
13 more elements
A method for performing floating-point addition using an asynchronous floating-point adder circuit, the method comprising:
- using an interleaved asynchronous adder as an adder component in order to perform floating-point addition in the asynchronous floating-point adder circuit, the interleaved asynchronous adder comprising two Ripple-Carry adders, a left Ripple-Carry adder and a right Ripple-Carry adder;
- said two Ripple-Carry adders being asynchronous circuits.
A method for performing floating-point addition using an asynchronous floating-point adder circuit, the method comprising:
- using an alignment shift component, the alignment shift component aligning significands of first and second inputs to the asynchronous floating-point adder circuit when exponents are different, aligned significands being adder inputs for floating-point addition,
- the alignment shift component comprising:
- a first shift component for a shift between zero and a predetermined bit position;
- a second shift component receiving output of said first shift component for a shift greater than the predetermined bit position and output of said first shift component for a shift between zero and the predetermined bit position;
- an output of the first shift component being provided directly to the merge component if the shift is between zero and the predetermined bit position.
2 more elements
Dependencies are inferred from the claim text.