Operand-optimized asynchronous floating-point units and method of use thereof
AssigneeCornell University
InventorsRajit Manohar, Basit R. Sheikh
Life of this patent
Estimating the term…
Abstract
Asynchronous arithmetic units including an asynchronous IEEE 754 compliant floating-point adder and an asynchronous floating point multiplier component. Arithmetic units optimized for lower power consumption and methods for optimization are disclosed.
Claims45
An asynchronous floating-point adder comprising:
- a front end component receiving a first input and second input, the first and second input being described in exponent/significand form;
- said front end analyzing the first and second input and obtaining a difference between an exponent of the first input and an exponent of the second input;
- said different comprising a difference in exponents;
- an alignment shift component receiving the difference in exponents;
- an adder component receiving adder inputs from said alignment shift component;
- a leading one predictor (LOP)/decoder component receiving adder inputs from said alignment shift component;
- a left shift/exponent adjustment determination component receiving an output of said adder component and an output of said leading one predictor/decoder component;
- a right shift/exponent adjustment determination component receiving an output of said adder component;
- and
- a left-right selection component;
- an output of said left-right selection component being utilized to provide an output of the asynchronous floating-point adder;
- said front end component, said shifter component, said adder component, said leading one predictor (LOP)/decoder component, said left shift/exponent adjustment determination component, said right shift/exponent adjustment determination component and said left right-selection component utilizing quasi-delay insensitive (QDI) asynchronous circuits;
- said front end component, said alignment shift component, said adder component, said leading one predictor (LOP)/decoder component, said left shift/exponent adjustment determination component, said right shift/exponent adjustment determination component and said left right-selection component being asynchronously pipelined;
- asynchronously pipelining enabling optimization of operand.
A fused multiply-adder comprising
- an alignment shifter receiving one adder input;
- a multiplier array receiving two multiplier inputs;
- and
- an adder receiving a processed output of the alignment shifter and a multiplier array output;
- said alignment shifter, said multiplier array and said adder utilizing quasi-delay insensitive (QDI) asynchronous circuits;
- and
- said alignment shifter, said multiplier array and said adder being asynchronously pipelined;
- asynchronously pipelining enabling optimization of the fused multiply-adder.
A method for improving energy efficiency of an asynchronous floating-point arithmetic unit, the method comprising:
- using operand characteristics for performance/energy optimization of the floating-point arithmetic unit.
A multiplier comprising:
- an unpacking component;
- the unpacking component unpacking a representation of multiplicands into sign, exponent and mantissa;
- an array multiplier component receiving mantissa bits for each input;
- the array multiplier generating partial products, providing the partial products to a number of carry-save adders and providing two bit streams as output;
- a carry propagation adder component receiving most significant bits of each of the two bit streams;
- a carry, round and sticky bit component receiving least significant bits of each of the two bit streams;
- and
- a round and normalization component receiving output from the carry propagation adder and the carry, round and sticky bit component;
- the array multiplier being asynchronously pipelined.
A method for improving energy efficiency of an asynchronous floating-point multiplier circuit, the method comprising using a single track handshake protocol in each template in each asynchronous pipeline, wherein asynchronous pipelines are used in components of the asynchronous floating-point multiplier circuit.
Dependencies are inferred from the claim text.