Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same

A multiplier circuit having first and second multi-bit multiplicand inputs and a multi-bit product output, comprising:

• a two-dimensional array of interconnected, substantially similar programmable logic blocks, each logic block comprising a multiply block and a programmable logic circuit driven by the multiply block, the logic circuit being programmed to implement an add function, the array comprising a first portion and a second portion, wherein:
• the array of logic blocks includes i rows and j columns, each logic block having X, Y, Z, Zi, Mi, and Ci inputs and P, Zo, Mo, and Co outputs, selecting one of Z or Zi as a Z′ input, implementing functions P=Y*Z′+X and Mo=Y*Z′, outputting a carry out signal on the Co output, and outputting Z′ as the Zo output;
• the first portion of the array is programmed as a partial product generator circuit coupled to receive the first and second multiplicand inputs, to provide a multi-bit partial product bus, and to provide lower bits of the product output;
• logic blocks in row 1 of the array are coupled to receive bits of the first multiplicand input at respective Z inputs, logic blocks in column 1, rows 1 through i-1, are coupled to receive bits of the second multiplicand input at respective Y inputs, the P outputs of the logic blocks in rows 2 through i, columns 2 through j-1, are coupled to the X inputs of logic blocks in rows 1 through i-1, columns 2 through j-1, respectively, logic blocks in row i are coupled to receive bit value 0 at the X inputs, logic blocks in row 1 are coupled to receive bit value 0 at the Zi, Mi, and Ci inputs, and logic blocks in rows 2 through i have Zi, Mi, and Ci inputs coupled to outputs Zo, Mo, and Co of the logic blocks in rows 1 through i-1, respectively;
• and
• the second portion of the array is programmed as an adder coupled to receive the partial product bus from the first portion of the array, and to provide from the partial product bus upper bits of the product output.

A method of implementing a multiplier having first and second multi-bit multiplicand inputs and a multi-bit product output in an integrated circuit, the method comprising:

• instantiating a two-dimensional array of substantially similar cells, nodes in adjacent cells being coupled one to another by abutment;
• wherein each cell comprises an M×N multiply block and a programmable logic circuit driven by the multiply block, N and M being integers greater than one;
• wherein the array of cells includes i rows and j columns, each cell having X, Y, Z, Zi, Mi, and Ci inputs and P, Zo, Mo, and Co outputs, selecting one of Z or Zi as a Z′ input, implementing functions P=Y*Z′+X and Mo=Y*Z′, outputting a carry out signal on the Co output, and outputting Z′ as the Zo output;
• configuring the cells in a first portion of the array to function as a partial product generator circuit coupled to receive the first and second multiplicand inputs, to provide a partial product bus, and to provide lower bits of the product output;
• wherein the instantiating of the cells includes coupling cells in row 1 of the array to receive bits of the first multiplicand input at respective Z inputs, coupling cells in column 1, rows 1 through i-1, to receive bits of the second multiplicand input at respective Y inputs, coupling the P outputs of the logic blocks in rows 2 through i, columns 2 through j-1, to the X inputs of logic blocks in rows 1 through i-1, columns 2 through j-1, respectively, coupling X inputs of the logic blocks in row i to receive bit value 0, coupling the Zi, Mi, and Ci inputs of the logic blocks in row 1 to receive bit value 0, and coupling Zi, Mi, and Ci inputs of logic blocks in rows 2 through i to outputs Zo, Mo, and Co of logic blocks in rows 1 through i-1, respectively;
• and
• configuring the cells in a second portion of the array to function as an adder coupled to receive the partial product bus from the first portion of the array, and to provide from the partial product bus upper bits of the product output.