G06F 2205/104
Delay lines
G06F2205/104 (Delay lines) appears on 30 US grants and 13 published applications in this corpus.
Search patents in G06F- Granted patents
- 30
- Published applications
- 13
- Assignees
- 21
- Inventors
- 61
- Latest grant
- 14 Dec 2021
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 3 | 0 |
| 1993 | 1 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 4 | 3 |
| 2002 | 4 | 2 |
| 2003 | 2 | 1 |
| 2004 | 1 | 0 |
| 2005 | 2 | 0 |
| 2006 | 1 | 3 |
| 2007 | 1 | 1 |
| 2008 | 1 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 2 | 2 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 1 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 1 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- Information processing apparatus, control method thereof, and non-transitory computer-readable storage medium14 Dec 2021US 11,201,622 B2Canon Kabushiki Kaisha
- Data rearranging circuit, variable delay circuit, fast fourier transform circuit, and data rearranging method7 Apr 2015US 9,002,919 B2NEC Corporation
- Method for reducing latency4 Sep 2012US 8,260,982 B2LSI Corporation
- Circuit and method for asynchronous pipeline processing with variable request signal delay29 May 2012US 8,188,765 B2International Business Machines Corporation
- Alignment mode selection mechanism for elastic interface28 Oct 2008US 7,443,940 B2International Business Machines Corporation
- Information processing apparatus, control method thereof, and non-transitory computer-readable storage medium29 Jul 2021US 2021/0234543 A1Canon Kabushiki Kaisha
- Data rearranging circuit, variable delay circuit, fast fourier transform circuit, and data rearranging method1 Nov 2012US 2012/0278373 A1NEC Corporation
- Circuit and method for asynchronous pipeline processing with variable request signal delay15 Mar 2012US 2012/0062300 A1International Business Machines Corporation
- System and method of transmitting data in an electronic circuit4 Jan 2007US 2007/0002634 A1
- Method for reducing latency7 Dec 2006US 2006/0277329 A1LSI Corporation
Most cited
By later US patents
- Computer system having memory device with adjustable data clocking91US 6,378,079 B1Micron Technology, Inc. · 2002
- Synchronous memory device having an adjustable data clocking circuit58US 6,327,196 B1Micron Technology, Inc. · 2001
- Asynchronous voice reconstruction for a digital communication system57US 5,103,467 AMotorola, Inc. · 1992
- Timing skew compensation technique for parallel data channels50US 6,874,097 B1Maxtor Corporation · 2005
- Method and apparatus for adjusting data timing by delaying clock signal45US 6,269,451 B1Micron Technology, Inc. · 2001