Method for reducing latency
AssigneeLSI Corporation
InventorsChristopher Paulson, Timothy Thompson, Kevin Campbell
Life of this patent
Estimating the term…
Abstract
Disclosed is a method for reducing latency between two clock domains in a digital electronic device. The time between a write to a queue position and a corresponding read of the queue position is reduced by up to one clock cycle by including a delay in the time before first writing data to a First In First Out (FIFO) queue used to buffer and synchronize data between two clock domains. The two clock domains have the same frequency, but may be out of phase. Reducing the latency between the write and the corresponding read reduces the required size of the FIFO queue and also results in more efficient system operation.
Claims11
A method for synchronizing data between two clock domains comprising the steps of:
- delaying a first data write to a FIFO queue from a first clock domain by up to one write clock cycle, and
- reducing latency between subsequent data writes to said FIFO queue and data reads from said FIFO queue into a second clock domain by said up to one write clock cycle, said first clock domain and said second clock domain having equivalent frequencies, said first clock domain and said second clock having any phase relationship with respect to each other.
A digital electronic device with multiple clock domains comprising:
- a write delay subsystem that delays a first data write to a FIFO queue from a first clock domain by up to one write clock cycle that reduces latency between subsequent data writes to said FIFO queue and data reads from said FIFO queue into a second clock domain by said up to one write clock cycle, said first clock domain and said second clock domain having equivalent frequencies, said first clock domain and said second clock having any phase relationship with respect to each other.
A digital electronic device with multiple clock domains comprising:
- means for delaying a first data write to a FIFO queue from a first clock domain by up to one write clock cycle;
- and
- means for reducing latency between subsequent data writes to said FIFO queue and data reads from said FIFO queue into a second clock domain by said up to one write clock cycle.
Dependencies are inferred from the claim text.