Method and apparatus for adjusting data timing by delaying clock signal

A clocked-data phase adjustment circuit comprising:

• a reference clock terminal adapted to receive a reference clock signal having a first state and a second state;
• a data terminal adapted to receive a data signal;
• and
• a phase shifting circuit adapted to receive a plurality of control signals, the reference clock signal, and the data signal each at respective inputs, the phase shifting circuit being adapted to adjust the time when the data signal is passed from the data input terminal to a data output terminal responsive to the phase of the reference clock signal, the phase of the reference clock signal being determined by the control signals, the phase shifting circuit including a plurality of passgates coupled in series with respective delay elements, each of the passgates being selectively controlled by at least one of the control signals to control the phase of the reference clock signal.

In a synchronous memory circuit, a circuit to adjust output data timing comprising:

• an external clock terminal adapted to receive an external clock signal having a first state and a second state;
• a clock filtering circuit coupled to the external clock terminal, the clock filtering circuit adapted to modifying the external clock signal into a data clock signal;
• a data terminal adapted to receive a data signal;
• an adjustable time delay circuit having a plurality of control inputs each receiving a respective control signal, the time delay circuit adapted to receive the data clock signal at a clock input and passing a time adjusted data clock signal to an output terminal, the time between when the data clock signal changes states and when the time adjusted data clock signal changes states determined by the control signals received at the control inputs, the adjustable time delay circuit including a plurality of passgates coupled in series with respective delay elements, each of the passgates being selectively controlled by at least one of the control signals to control the phase of the time adjusted data clock signal relative to the phase of the data clock signal;
• and
• a data passing circuit adapted to receive both the data signal and the time adjusted data clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal after the time adjusted data clock signal changes from the first to the second state.

A method of adjusting the time that data is delivered to an output terminal of a memory circuit after the memory circuit has been fabricated, the method comprising the steps of:

• accepting a data signal at a data input;
• accepting a clock signal at a clock input;
• selecting a delay time to be added to the clock signal to generate a delayed clock signal, the delay time being selected by selectively coupling control inputs to a control voltage, the control inputs coupled to and controlling a plurality of passgates such that for any single pattern of coupled control inputs, there exists only one path through a controllable delay circuit;
• and
• using the delayed clock signal to control the time when the data signal is passed to a data output.