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US 8,260,982 B2Granted
Method for reducing latency
AssigneeLSI Corporation
InventorsChristopher D. Paulson, Timothy D. Thompson, Kevin T. Campbell
Life of this patent
Estimating the term…
Abstract
Disclosed is a method for reducing latency between two clock domains in a digital electronic device. The time between a write to a queue position and a corresponding read of the queue position is reduced by up to one clock cycle by including a delay in the time before first writing data to a First In First Out (FIFO) queue used to buffer and synchronize data between two clock domains. The two clock domains have the same frequency, but may be out of phase. Reducing the latency between the write and the corresponding read reduces the required size of the FIFO queue and also results in more efficient system operation.
Claims11
A method for synchronizing data between two clock domains comprising:
- delaying a first data write to a FIFO queue from a first (write) clock domain by up to one write clock cycle thereby reducing latency between subsequent data writes to said FIFO queue and data reads from said FIFO queue into a second (read) clock domain by said up to one write clock cycle, said first (write) clock domain and said second (read) clock domain having equivalent frequencies, said first (write) clock domain and said second (read) clock domain having any phase relationship with respect to each other;
- delaying a first data read of said FIFO queue by up to a first read clock cycle occurring after said up to one write clock cycle to achieve a meta-stable data storage condition;
- writing a first data element into a first position of said FIFO queue;
- delaying said first data read of said FIFO queue by up to a second read clock cycle to achieve a stable data storage condition;
- reading said first data element from said first position of said FIFO queue;
- writing data to each position in said FIFO queue by writing data to a position in said FIFO queue on a write clock cycle and writing to a next position of said FIFO queue on a next write clock cycle, said next position of said FIFO queue being said first position of said FIFO queue when a last position of said FIFO queue was written on said write clock cycle;
- and
- reading each written data position in said FIFO queue less than two read clock cycles after said written data position of said FIFO queue receives data from said first (write) clock domain.
5 more elements
A digital electronic device with multiple clock domains comprising:
- a write delay subsystem that delays a first data write to a FIFO queue from a first (write) clock domain by up to one write clock cycle that reduces latency between subsequent data writes to said FIFO queue and data reads from said FIFO queue into a second (read) clock domain by said up to one write clock cycle, said first (write) clock domain and said second (read) clock domain having equivalent frequencies, said first (write) clock domain and said second (read) clock domain having any phase relationship with respect to each other;
- a read delay subsystem that delays a first read of said FIFO queue by up to two read clock cycles after said up to one write clock cycle in order to achieve a stable data storage condition;
- a write data subsystem that writes data to a position of said FIFO queue starting at a first position of said FIFO queue, said write data subsystem writing data to each position in said FIFO queue by writing data to a position in said FIFO queue on a write clock cycle and writing to a next position of said FIFO queue on a next write clock cycle, said next position of said FIFO queue being said first position of said FIFO queue when a last position of said FIFO queue was written on said write clock cycle;
- and
- a read data subsystem that reads each written data position in said FIFO queue less than two read clock cycles after said written data position of said FIFO queue receives data from said write data subsystem.
2 more elements
A digital electronic device with multiple clock domains comprising:
- means for delaying a first data write to a FIFO queue from a first (write) clock domain by up to one write clock cycle, said first (write) clock domain and said second (read) clock domain having equivalent frequencies, and said first (write) clock domain and said second (read) clock domain having any phase relationship with respect to each other;
- means for delaying a first data read of said FIFO queue by up to a first read clock cycle occurring after said up to one write clock cycle;
- means for writing a first data element into a first position of said FIFO queue;
- means for delaying said first data read of said FIFO queue by up to a second read clock cycle;
- means for reading said first data element from said first position of said FIFO queue;
- means for writing data to each position in said FIFO;
- and
- means for reading each written data position in said FIFO queue less than two read clock cycles after said written data position of said FIFO queue receives data from said first (write) clock domain.
5 more elements
Dependencies are inferred from the claim text.