Alignment mode selection mechanism for elastic interface

A method for receiving a transmission of digital data in an elastic interface system, the method comprising the steps of:

• receiving a clock/data group on a bus resulting in a received clock/data group, wherein the received clock/data group includes:
• a clock signal, wherein the clock signal includes a plurality of clock edges;
• and
• a plurality of data bits, wherein the plurality of data bits includes even data beats, odd data beats, a latest data bit, and wherein corresponding bits of the clock signal and the plurality of data bits are launched onto the bus substantially simultaneously;
• delaying the plurality of data bits individually to center data windows with a nearest of the plurality of clock edges, to result in a plurality of de-skewed data bits;
• determining the latest data bit from the plurality of de-skewed data bits;
• if the latest data bit was delayed to center its data windows to a rising edge of the clock signal, loading even data beats into a plurality of even FIFO latches;
• and
• if the latest data bit was delayed to center its data windows to a falling edge of the clock signal, loading even data beats into a plurality of odd FIFO latches;
• determining whether the latest data bit was delayed to center its data windows with the plurality of rising clock edges or the plurality of falling clock edges;
• if an align-to-falling-edge mode has been selected and the latest data bit was delayed to center its data windows with the plurality of all falling clock edges, loading the latest data bit's plurality of even data beats into a plurality of odd FIFO latches;
• delaying a plurality of earlier de-skewed data bits to result in a plurality of aligned, earlier data bits, wherein the plurality of aligned, earlier data bits have corresponding data beats aligned with corresponding data beats of the latest data bit;
• and
• loading even data beats for the plurality of aligned, earlier data bits into the plurality of odd FIFO latches, wherein the step of loading even data beats for the plurality of aligned, earlier data bits occurs concurrently with the step of loading the latest data bit's plurality of even data beats into the plurality of odd FIFO latches;
• wherein the step of delaying the latest data bit is accomplished by sending the latest data bit through a latch.

A circuit for receiving a transmission of digital data in an elastic interface system, the circuit comprising:

• a receiver for receiving a clock/data group on a bus resulting in a received clock/data group, wherein the received clock/data group comprises:
• a clock signal, wherein the clock signal includes a plurality of clock edges;
• and
• a plurality of data bits, wherein each of the plurality of data bits includes a plurality of even data beats, odd data beats, a latest data bit, and wherein corresponding bits of the clock signal and the plurality of data bits are launched onto the bus substantially simultaneously;
• a first delay line for delaying the plurality of data bits individually to center data windows with a nearest of the plurality of clock edges, to result in a plurality of de-skewed data bits;
• a first logic circuit for determining a latest data bit from the plurality of de-skewed data bits;
• a second logic circuit for determining an alignment mode selection;
• a third logic circuit for loading the latest data bit's plurality of even data beats into a plurality of even FIFO latches if:
• the alignment mode selection is align-to-closest-edge;
• and
• the latest data bit was delayed to center its data windows with the plurality of rising clock edges;
• a fourth logic circuit for loading the latest data bit's plurality of even data beats into a plurality of odd FIFO latches if:
• the alignment mode selection is an align-to-closest-edge mode;
• and
• the latest data bit was delayed to center its data windows with the plurality of falling clock edges;
• second delay line for delaying the latest bit by a first delay time to result in a delayed, latest bit if the latest data bit was delayed to center its data windows with the plurality of falling clock edges, wherein:
• the first delay time facilitates loading even data beats of the delayed, latest bit into even FIFO latches in response to the plurality of rising clock edges;
• and
• the first delay time is less than or equal to three bit times of the clock signal.