Data rearranging circuit, variable delay circuit, fast fourier transform circuit, and data rearranging method
AssigneeNEC Corporation
InventorsYuki Kobayashi, Katsutoshi Seki
Life of this patent
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Abstract
A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.
Claims8
A data rearranging circuit comprising:
- variable delay means that, by giving to each unit of data of a data group that is applied as input to a plurality of ports in a plurality of cycles, a delay of a number of delay cycles that differs for each input cycle, and moreover, for each port, switches order of data in the same port and supplies the result as the data group at a predetermined delay;
- control means that supplies control information that includes said number of delay cycles that is used in the variable delay means;
- and
- shuffle means that is connected to a stage before and after said variable delay means, that switches, among ports in the same cycle, data applied as input to a plurality of ports in a plurality of cycles, and that supplies the result as output,
- wherein shuffle information that indicates switching in said shuffle means is further included in said control information that is supplied by said control means.
A data rearrangement method comprising:
- generating control information that includes a number of delay cycles that differs for each input cycle and moreover for each port, the control information being established such that order of data in the same port for each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles is switched and the data group has a predetermined delay;
- based on said control information, giving to input data a delay of a number of delay cycles that differs for each input cycle and moreover for each port and supplying the result;
- and
- in a stage before or after giving said delay, switching, among ports in the same cycle, data applied as input to a plurality of ports in a plurality of cycles, and supplying the result as output,
- wherein shuffle information which controls the switching is further included in said control information.
Dependencies are inferred from the claim text.