Timing skew compensation technique for parallel data channels
AssigneeMaxtor Corporation
InventorsMehran Aliahmad, Russell W Brown, Bruce Leshay
Life of this patent
Estimating the term…
Abstract
A method and apparatus for correcting the timing skew of data signals in a parallel data transmission system, such as Small Computer System Interface (SCSI) data bus, relative to a receive clock in the data bus. The system separately corrects the receive clock duty cycle, and also features independent de-skewing of the rising and falling edges of a data waveform to improve timing accuracy of transmitted signals. The method and apparatus can be used without substantial changes to existing transmission system protocols, and can be implemented on an all-digital integrated circuit.
Claims45
An apparatus for detecting and correcting the timing skew of a data signal in a parallel data transmission system, comprising:
- a data path for adjusting the timing skew of the data signal with respect to a clock signal, said data path including:
- a delay digital-to-analog converter (DAC), a falling edge DAC, at least two receive registers, an output multiplexer, and control logic;
- a clock path for correcting the duty-cycle of a receive clock and for delaying said receive clock in normal receive operations, wherein said clock path is selectably switchable between a timing skew correction mode and a receive-data mode;
- a local accurate tuning system for generating a timing signal to tune all of the delay elements of said parallel data transmission system according to a bit-cell time of the data signal;
- wherein said control logic detects the timing skew of the data signal and controls said delay DAC and said falling edge DAC to provide appropriate delay to the data signal in accordance with the detected timing skew of said data signal.
An apparatus for detecting and correcting the timing skew of data in a parallel data transmission system having a receive clock and at least one data signal with a bit-cell time, the apparatus comprising:
- a local accurate tuning system configured to generate a tuning signal according to the bit-cell time;
- a clock path configured to correct the duty-cycle of the receive clock according to said tuning signal and said bit-cell time, wherein said clock path is selectably switchable between a timing skew correction mode and a receive-data mode;
- a data path in parallel with said clock path comprising:
- a delay digital-to-analog converter (DAC), a falling edge DAC, at least two receive registers, an output multiplexer, and control logic;
- said control logic detecting the timing skew of said at least one data signal and controlling said delay DAC and said falling edge DAC to provide appropriate delay to said data signal in accordance with the detected timing skew of said data signal with respect to said clock signal;
- said delay DAC delaying said at least one data signal according to said tuning signal and instructions from said control logic;
- said falling-edge DAC delaying the falling edges of said at least one data signal according to said tuning signal and instructions from said control logic;
- said receive registers capturing data on both the rising and falling edges of said clock signal;
- said output multiplexer swapping the outputs of said at least two receive registers according to instructions from said control logic.
A method for detecting and correcting the timing skew of data in a parallel data transmission system having a receive clock and at least one data signal with a bit-cell time, the method comprising:
- generating a tuning signal having an amplitude based on a local accurate clock;
- correcting the duty-cycle of the receive clock according to said tuning signal and the bit-cell time;
- determining the time delay of said at least one data signal relative to the receive clock and said tuning signal;
- adjusting the time delay of said at least one data signal relative to the receive clock;
- adjusting the time delay of falling edges of said at least one data signal relative to said receive clock;
- capturing data from said at least one data signal on the rising and falling edges of said receive clock;
- and
- swapping the outputs of at least two receive registers used in said capturing if the detected time-skew of said at least one data signal reaches a predetermined level.
An apparatus implemented on an integrated circuit for detecting and correcting the timing skew of at least one data signal in a parallel data transmission system, comprising:
- a local accurate tuning system for generating a direct current (DC) tuning signal according to a bit-cell time of said parallel data transmission system;
- a clock path for adjusting the timing and duty-cycle of a receive clock according to said DC tuning signal and said bit-cell time, wherein said clock path is selectably switchable between a timing skew correction mode and a receive-data mode;
- a data path positioned in parallel with said clock path comprising:
- a delay digital-to-analog converter (DAC), a falling edge DAC, at least two receive registers, an output multiplexer, and control logic;
- said control logic detecting the timing skew of at least one data signal and controlling said delay DAC and said falling edge DAC to provide appropriate delay to said data signal in accordance with the detected timing skew of said data signal with respect to said receive clock;
- wherein said apparatus is implemented on the receive-side of said parallel data transmission system and operates substantially without control of the transmission side of said parallel data transmission system.
Dependencies are inferred from the claim text.