G06F 13/18
Based on priority control
Official title: based on priority control (G06F13/1605 takes precedence)
G06F13/18 (Based on priority control) appears on 728 US grants and 437 published applications in this corpus.
Search patents in G06F- Granted patents
- 728
- Published applications
- 437
- Assignees
- 238
- Inventors
- 1,373
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 12 | 0 |
| 1977 | 15 | 0 |
| 1978 | 10 | 0 |
| 1979 | 10 | 0 |
| 1980 | 10 | 0 |
| 1981 | 9 | 0 |
| 1982 | 11 | 0 |
| 1983 | 17 | 0 |
| 1984 | 10 | 0 |
| 1985 | 13 | 0 |
| 1986 | 17 | 0 |
| 1987 | 12 | 0 |
| 1988 | 12 | 0 |
| 1989 | 17 | 0 |
| 1990 | 7 | 0 |
| 1991 | 6 | 0 |
| 1992 | 8 | 0 |
| 1993 | 3 | 0 |
| 1994 | 3 | 0 |
| 1995 | 17 | 0 |
| 1996 | 15 | 0 |
| 1997 | 22 | 0 |
| 1998 | 23 | 0 |
| 1999 | 10 | 0 |
| 2000 | 17 | 0 |
| 2001 | 19 | 3 |
| 2002 | 6 | 10 |
| 2003 | 14 | 6 |
| 2004 | 10 | 5 |
| 2005 | 4 | 9 |
| 2006 | 6 | 1 |
| 2007 | 4 | 4 |
| 2008 | 2 | 4 |
| 2009 | 4 | 5 |
| 2010 | 5 | 1 |
| 2011 | 5 | 6 |
| 2012 | 2 | 46 |
| 2013 | 9 | 11 |
| 2014 | 30 | 20 |
| 2015 | 30 | 27 |
| 2016 | 29 | 27 |
| 2017 | 22 | 19 |
| 2018 | 15 | 34 |
| 2019 | 35 | 47 |
| 2020 | 42 | 21 |
| 2021 | 26 | 19 |
| 2022 | 20 | 19 |
| 2023 | 19 | 21 |
| 2024 | 21 | 27 |
| 2025 | 24 | 26 |
| 2026 | 19 | 19 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Dynamic priority inversion for host memory buffer handling based on a system state6 Oct 2026US 12,754,863 B2SanDisk Technologies LLC
- Data coding device, memory controller, and storage device29 Sep 2026US 12,748,708 B2SK hynix Inc.
- Optimized prioritization of memory accesses25 Aug 2026US 12,717,729 B2Intel Corporation
- Quality of service control for read operations in memory systems11 Aug 2026US 12,704,998 B2Micron Technology, Inc.
- Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures—memory barriers16 Jun 2026US 12,657,023 B2NVIDIA Corporation
- Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures – memory barriers17 Sep 2026US 2026/0277607 A1NVIDIA Corporation
- Cache flush operations17 Sep 2026US 2026/0277818 A1Micron Technology, Inc.
- Time-Independent Scheduling Of Operations In A Storage System23 Jul 2026US 2026/0211823 A1Pure Storage, Inc.
- Integrated circuit and method for data transmission, medium, device, and chip2 Jul 2026US 2026/0186991 A1Beijing Horizon Robotics Technology Research and Development Co., Ltd.
- Communication control device for a subscriber station of a serial bus system and method for handling messages in a subscriber station of a serial bus system25 Jun 2026US 2026/0178521 A1
Most cited
By later US patents
- Dual port ram with arbitration status register235US 4,937,781 ADallas Semiconductor Corporation · 1990
- Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue232US 5,623,628 AIntel Corporation · 1997
- Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same227US 4,276,594 AGould Inc., Modicon Division · 1981
- Hierarchical multi-processor network for memory sharing220US 4,240,143 ABurroughs Corporation · 1980
- Priority encoding and decoding for memory architecture207US 6,006,303 AOki Electric Industry Co., Ltd. · 1999