Dual port ram with arbitration status register
AssigneeDallas Semiconductor Corporation
InventorsRobert D. Lee, Hal Kurkowski
Life of this patent
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Abstract
A dual port RAM includes an arbiter (10) which interfaces between a random access memory (12) and two ports, a serial port (19) and a parallel port (21). The arbiter (10) has an internal arbitration byte (38) for storing status information. The arbiter operates in first and second modes. In the first mode, the serial port (19) is afforded priority access to the system with status information stored in the arbitration byte (38). The parallel port (21) polls the arbitration byte (38) to determine the system status. In the second mode, the first port to attempt access is provided priority and this information is stored in the arbitration byte (38). In this mode, each port attempting access must poll the arbitration byte (38) before attempting access.
Claims22
A duel port RAM, comprising:
- a first port for receiving an address and for transfer of data;
- a second port for receiving an address and for transfer of data;
- an array of memory locations for storing data, each of said memory locations having an array address associated therewith;
- and
- arbitration means for receiving addresses from said first port and determining if the received address from said first port is an array address,
- said arbitration means being operable to transmit addresses from said first port to said array and transfer data between said first port and said array when the received address from said first port is an array address, and
- said arbitration means being operable to transmit addresses from said second port to said array and transfer data between said second port and said array when an array address is not received from said first port;
- arbitration storage means for storing arbitration status information of said arbitration means, said arbitration storage means having a predetermined address associated therewith, said predetermined address being continuous with the sequence of said array addresses;
- said arbitration means including:
- match means for receiving addresses from said first and second ports and determining if said addresses from said first or second ports match said predetermined address, and
- access means for accessing said arbitration storage means when said match means determines that said arbitration address is received from either said first port or said second port, said access means transmitting said arbitration status information from said arbitration storage means to the one of said first and second ports from which said arbitration address was received.
A multi-port RAM, comprising:
- an array of memory locations for storing data, each of said memory locations having an address associated therewith;
- a plurality of ports, each for receiving an address and for transfer of data;
- an arbitration memory location for storing arbitration status information, said arbitration memory location having an arbitration address associated therewith, said arbitration address being continuous with the sequence of said memory locations of said array;
- data/address transfer means for selecting one of said ports to access said array and transferring the address received by the selected one of said ports to said array and transferring data between the selected one of said ports and said array;
- compare means for comparing said received address on each of said ports with an internally stored reference arbitration address, said compare means making a true comparison when the address compared to said reference arbitration address is said arbitration address;
- arbitration access means for accessing said arbitration memory location in response to said compare means making a true comparison, said arbitration access means outputting said arbitration status information to the one of said ports from which said arbitration address was received;
- and
- priority means, connected to see addresses received at said ports, for determining the priority of each of said ports in accordance with a predetermined priority status when an address other than said arbitration address is received from any one of said ports, said priority means controlling said data/address transfer means to select the highest priority one of said ports that receives an address other than said arbitration address.
A method for accessing an array of separately addressable memory locations from one of a plurality of ports for transfer of data between the plurality of ports and the array in accordance with addresses received at the ports, comprising the steps of:
- providing an internal register for storing arbitration status information, the internal register having an arbitration address associated therewith;
- comparing the received address on each of the ports with an internally stored reference arbitration address, a true comparison made when the address compared to the reference arbitration address is the arbitration address;
- accessing the internal register in response to a true comparison being made and outputting the arbitration status information to the one of the ports from which the arbitration address was received;
- determining the priority of each of the ports in accordance with a predetermined priority status when an address other than the arbitration address is received from any one of the ports;
- and
- selecting the highest priority one of the ports that receives an address other than the arbitration address and transferring the address received by the selected one of the ports to the array and transferring data between the selected one of the ports and the array.
Dependencies are inferred from the claim text.