Optimized prioritization of memory accesses
AssigneeIntel Corporation
InventorsSai Prashanth Muralidhara, Narasimha Sridhar Srirangam, Rawan Abdel Khalek, Yedidya Hilewitz, Daniel Liu, Sharada Venkateswaran, Wolf Witt, Nishant Singh
Life of this patent
Estimating the term…
Abstract
Embodiments described herein may include apparatus, systems, techniques, or processes that are directed prioritizing memory requests from core processors such that some memory transaction requests receive a higher priority than other memory transaction requests. In some embodiments, queue lengths and latency, frequency of core demand transaction prioritization and the like are monitored and prioritization throttled accordingly. Other embodiments may be described and/or claimed.
Claims19
A system comprising:
- a memory;
- and
- core circuit communicatively coupled to the memory, the core circuit comprising:
- a processing core;
- and
- a prioritization circuit to receive a memory transaction request from the processing core, the memory transaction request including source information identifying at least a type of source of the memory transaction request, the prioritization circuit further to determine and set a priority level of the memory transaction request based at least in part on the source information, the prioritization circuit further to send the memory transaction request with the priority level to the memory.
An apparatus comprising:
- a processing core;
- and
- a prioritization circuit to receive a memory transaction request from the processing core, the memory transaction request including source information identifying at least a type of source of the memory transaction request, the prioritization circuit further to determine and set a priority level of the memory transaction request based at least in part on the source information, the prioritization circuit further to send the memory transaction request with the priority level to the memory.
A method comprising:
- receiving a memory transaction request from a processing core, the memory transaction request including source information identifying at least a type of source of the memory transaction request;
- determining and setting a priority level of the memory transaction request based at least in part on the source information;
- and
- sending the memory transaction request with priority information to a memory controller.
Dependencies are inferred from the claim text.