Data coding device, memory controller, and storage device

A storage device comprising:

• a memory device;
• a command manager configured to manage whether or not to perform a command received from an external command;
• and
• a command processor configured to receive and process the command according to a priority from the command manager,
• wherein the command manager comprises:
• a plurality of slots receiving a command input from an external host;
• and
• a performance management circuit including counter circuits respectively corresponding to the plurality of slots, activating a counter circuit corresponding to a slot to which the command is input among the plurality of slots in response to an input of the command, switching the counter circuit to an expiration state when a preset time is exceeded without a response corresponding to the command being provided to the host, providing an interrupt signal requesting processing of the command to the command processor in response to the expiration state of the counter circuit, and deactivating the counter circuit when a response corresponding to the command is completed from the slot.