Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures—memory barriers
AssigneeNVIDIA Corporation
InventorsTimothy Ian Milne, Vaishali Kulkarni, Debajit Bhattacharya, Ashish Kumar Maurya, Tong Tong, Vadiraj Alias Abhay Ayachit, Chase Caldwell Wheeler
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Abstract
This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and/or a hardware-implemented memory barrier capability.
Claims18
A multi-dielet processing system comprising:
- a plurality of processors on respectively different dielets, comprising at least a first processor on a first dielet and a second processor on a second dielet, wherein the plurality of processors each comprises at least one hardware engine;
- a respective memory barrier handling circuit arranged on each of the first and second dielets, wherein each memory barrier handling circuit is configured to determine a state of a memory barrier based on acknowledgements received from the same dielet and one or more acknowledgements received from other dielets;
- and
- a memory barrier trigger register,
- wherein each memory barrier handling circuit is further configured to, in response to the memory barrier trigger register, initiate the memory barrier.
A multi-dielet processing system comprising:
- a plurality of processors on respectively different dielets, comprising at least a first processor on a first dielet and a second processor on a second dielet, wherein the plurality of processors each comprises at least one hardware engine;
- a respective memory barrier handling circuit arranged on each of the first and second dielets, wherein each memory barrier handling circuit is configured to determine a state of a memory barrier based on acknowledgements received from the same dielet and one or more acknowledgements received from other dielets;
- a respective frame buffer hub unit arranged on each dielet of the respectively different dielets;
- and
- a high priority direct interface connecting frame buffer hub units on all dielets of the respectively different dielets,
- wherein each memory barrier handling circuit is configured to communicate with other memory barrier handling circuits over the high priority direct interface.
A multi-dielet processing system comprising:
- a plurality of processors on respectively different dielets, comprising at least a first processor on a first dielet and a second processor on a second dielet, wherein the plurality of processors each comprises at least one hardware engine;
- and
- a respective memory barrier handling circuit arranged on each of the first and second dielets, wherein each memory barrier handling circuit is configured to determine a state of a memory barrier based on acknowledgements received from the same dielet and one or more acknowledgements received from other dielets, wherein each memory barrier handling circuit is further configured to implement a remote flush request-acknowledgment handshake over a direct interface for pushing remote dielet traffic to a system level point of coherency.
A multi-dielet processing system comprising:
- a plurality of processors on respectively different dielets, comprising at least a first processor on a first dielet and a second processor on a second dielet, wherein the plurality of processors each comprises at least one hardware engine;
- a respective memory barrier handling circuit arranged on each of the first and second dielets, wherein each memory barrier handling circuit is configured to determine a state of a memory barrier based on acknowledgements received from the same dielet and one or more acknowledgements received from other dielets;
- and
- a hardware engine remapping circuitry comprising a plurality of dielet-level remapping circuits, and each dielet of the respectively different dielets includes a respective one of the dielet-level remapping circuits, wherein each of the dielet-level remapping circuits is configured to map between respective local engine identifiers of the hardware engines and corresponding respective unique engine identifiers.
A method performed by a dielet-level remapping circuitry in a dielet in a multi-dielet processing system comprising (a) processors on respectively different dielets each comprising hardware engines and (b) a respective dielet-level remapping circuitry, including performing operations comprising:
- changing state of a memory barrier based on acknowledgements received from circuits on the dielet;
- changing state of the memory barrier based on and one or more acknowledgements received from circuits on other dielets;
- and
- mapping between respective local engine identifiers of the hardware engines and corresponding respective unique engine identifiers.
Dependencies are inferred from the claim text.