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US 4,240,143 AGranted
Hierarchical multi-processor network for memory sharing
AssigneeBurroughs Corporation
InventorsJohn O. Besemer, Clifford J. Bellamy
Life of this patent
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AssigneeBurroughs Corporation
InventorsJohn O. Besemer, Clifford J. Bellamy
Estimating the term…
A plurality of processors and memory modules arranged in a hierarchy are connected in a network such that memory sharing can occur during processor operations, and control means are provided so as to regulate protected usage of specific areas of the memory modules. A Global Memory Module (GMM) and a system hierarchy of processors is described which provides access to a plurality of addressable memory storage units. A multiple number of processors or computer systems are connected to one or more Global Memory Modules whereby memory resources may be shared by multiple processor systems and where control and communications are provided between the processors through the Global Memory Modules. The Global Memory Module may be organized into a hierarchy of Global Memory Module systems whereby processors attached to "lower level" GMM systems may access memory in "higher level" GMM systems. Means are provided whereby a processor in one GMM system may send commands and messages to a processor in another GMM system. Means are provided by which one processor can address another specific processor in the system network or whereby one processor can address an "available" processor in a system designated under a system name, and the network will choose the processor which is "idle" or, if there is no idle processor available, will then choose a processor which is "not engaged", that is to say, a processor which when it finishes its currently scheduled activities, will then be available for processing of a received command and message.
In a network for the coupling of processor-groups, forming a system "III" to processor-groups forming a system "II", to processor-groups forming a system "I", to processor-groups forming a system "0", and wherein each of said processor-groups includes processors having individual bus connections to a common memory-communication-coupling module unique to that system to form a single system "X", and wherein a plurality of memory-communication-coupling modules of systems X . . . II, I, 0 are interconnected in order to establish higher level and lower level systems whereby processors in higher level systems are master over processors in lower level systems, thus to establish a hierarchy of systems, and wherein said memory-communication-coupling modules in each system have memory storage units which are organized to provide a numerically hierarchical system of address values wherein each higher level system will have memory storage units with addresses of a higher number than the memory storage units in lower level systems, the network comprising:
Dependencies are inferred from the claim text.