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US 2026/0277607 A1Published application
Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures – memory barriers
AssigneeNVIDIA Corporation
InventorsTimothy Ian MILNE, Vaishali KULKARNI, Debajit BHATTACHARYA, Ashish Kumar MAURYA, Tong TONG, Vadiraj Alias Abhay AYACHIT, Chase Caldwell WHEELER
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Abstract
This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and/or a hardware-implemented memory barrier capability.
Claims1
A multi-dielet processing system comprising:
- a plurality of processors on respectively different dielets, comprising at least a first processor on a first dielet and a second processor on a second dielet, wherein the plurality of processors each comprises at least one hardware engine;
- and
- a respective memory barrier handling circuit arranged on each of the first and second dielets, wherein each memory barrier handling circuit is configured to determine a state of a memory barrier based on acknowledgements received from the same dielet and one or more acknowledgements received from other dielets.
Dependencies are inferred from the claim text.