US 4,276,594 A · Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same

Abstract

A digital computer with the capability of incorporating multiple central processing units (CPU's), utilizes an address and data bus between each central processing unit and from one to fifteen intelligent composite memory and input/output modules (MIO). Data is transferred to and from each MIO and the CPU synchronously by a bus during one phase of a three phase clocking cycle. During a second phase of the clocking cycle data on one or more low speed serial data channels within each MIO is transferred to and from the MIO and external devices. During the third phase of the clocking cycle data on a high speed direct memory access channel (DMA) is transferred to and from the MIO and one or more external devices. Additional CPU's can be interconnected with the first CPU by means of an inter-processor buffer module (IPB) which interconnects to the bus at one end and the additional CPU, by means of a bus, at its other end. The IPB may be a software modifiable MIO and can store data addressable by the two interconnected CPU's. In turn, the additional CPU and its associated bus interconnects by the second bus with from one to fifteen additional MIO's or IPB's, allowing cascading of CPU's and associated MIO's and IPB's. Since all data transfers to and from the MIO's and external devices occur at time phases separate from the first time phase in which the CPU communicates with the MIO's and IPB's, the computational speed of any CPU is independent of the quantity of data transferred between the MIO's and IPB's and associated external devices or additional CPU's.

Claims36

Dependent claims

A computer comprising:

(A) a central processing unit (CPU) for the processing of data, the CPU having a processor;
(B) means, connected to the CPU for providing a communication path to and from the CPU;
(C) a clock, connected to the communication path means, for generating a repetitive multi-phase clock cycle;
and
(D) a composite, intelligent memory and input/output module (MIO), connected to the communication path means, so as to store and transfer data to and from the CPU and to and from external devices, the data including all application code for execution by the CPU as well as all data used in the execution of the application code, the MIO comprising:
(1) a public memory for the storage of data accessible to both the CPU and the external devices during different phases of the multiphase clock cycle,
(2) a microprocessor responsive to the phases of the multi-phase clock cycle so as to control public memory access by the CPU and the external devices,
(3) a microprocessor bus connecting the public memory to the microprocessor,
(4) means, responsive to the microprocessor and connected to the microprocessor bus, for interfacing data to and from the external devices with the public memory, and
(5) means, responsive to the microprocessor and connected between the public memory and the communication path means, for interfacing data to and from the public memory and the CPU;
whereby data transfer to and from the public memory of the MIO to the communication path means occurs during a distinct phase of the clock cycle and the transfer of data to and from the public memory of the MIO with the external devices occurs during another distinct phase of the clock cycle.

8 more elements

A digital computer comprising:

(A) a first central processing unit (CPU);
(B) a bus interconnected to the central processing unit;
(C) a clock, interconnected to the bus, for repetitively generating at least two distinct clock phases per generation of a clock cycle;
and
(D) up to N composite, intelligent memory, and input/output modules (MIO's), each interconnected to the bus, N being a positive integer greater than one, and each MIO having,
(1) a public memory for the storage of data including application code for execution by the CPU and data used in the execution of the application code accessible to both the CPU and external devices during different phases of the cycle,
(2) a first buffer for data transferral from the public memory to the bus,
(3) a second buffer for data transferral from the public memory to interconnected external devices, and
(4) means, responsive to the clock phases and communicating with the first and second buffers, for controlling the access to and from the public memory by the CPU during one clock cycle phase and for providing access to and from the public memory by external devices during at least one other clock cycle phase;
whereby data transfer to and from the public memory of each MIO to the bus occurs during a distinct phase of the clock cycle and the transfer of data to and from the public memory of each MIO with external devices occurs during another distinct phase of the clock cycle.

7 more elements

A digital computer comprising:

(A) at least first and second central processing units (CPU's),
(B) a first bus connected to the first central processing unit,
(C) a second bus connected to the second central processing unit,
(D) a clock for generating a repetitive clock cycle having at least first and second distinct clock phases per clock cycle;
and
(E) an interprocessor buffer (IPB) having
(1) a first public memory for the storage of data, the data including the application code for execution by the first CPU as well as the data used in the execution of this application code accessible to both the first and second CPU's during different phases of the clock cycle,
(2) means, connected to the first bus and to the first public memory, for providing data transfer to and from the first bus and the first public memory,
(3) means, connected to the second bus and to the first public memory, for providing data transfer to and from the second bus and the first public memory, and
(4) a first microprocessor responsive to the phases of the clock cycle for at least control of first public memory access by the first CPU via the first bus and first bus transfer means during the first clock phase and public memory access to the first public memory by the second CPU via the second bus and second bus transfer means during the second clock phase;
and
(F) at least one composite intelligent memory and input/output module (MIO), connected to the second bus so as to store and transfer data to and from the second CPU and to and from external devices, the data, in combination with the data in the first public memory, including all application code for execution by the second CPU as well as all data used in the execution of the application code, the MIO comprising:
(1) a second public memory for the storage of data accessible to both the second CPU and the external devices during different phases of the repetitive clock cycle,
(2) a second microprocessor responsive to the phases of the repetitive clock cycle so as to control memory access to the second public memory by the second CPU and the external devices,
(3) a microprocessor bus connecting the second public memory to the microprocessor,
(4) means, responsive to the microprocessor and connected to the microprocessor bus, for interfacing data to and from the external devices with the second public memory, and
(5) means, responsive to the microprocessor and connected between the second public memory and the second bus, for interfacing data to and from the second public memory and second bus;
whereby data transfer to and from the first public memory with the first and second buses occurs during distinct phases of the clock cycle and the transfer to and from the second public memory with external devices and the second bus occurs also during distinct phases of the clock cycle.

15 more elements

A method of processing and transferring data between a first location and a second location interconnected thereto by a bus and between the second location and communicating external devices, comprising the steps of:

(1) processing data, including specifying and executing application code at the first location;
(2) generating repetitive clock cycles, each clock cycle having at least first, second, and third distinct clock phases;
(3) reading all data necessary for specifying and executing application code from any of up to N second locations at the first location, where N is a positive integer, by performing the following substeps:
(a) during the third phase of the clock cycles informing any second location of an address within that particular second location where data is to be read by the first location,
(b) during the first phase of the clock cycles transferring data from the selected address location of the second location defined in Step 3a to the bus interconnecting the first location with each second location, and
(c) during the second phase of the clock cycles reading at the first location the data placed on the bus by the selected second location defined in Step 3a during the first phase of the clock cycle,
(4) writing data from the first location with any of up to the N second locations by performing the following substeps:
(a) during the first phase of the clock cycles putting an address on the bus by the first location, the address representing a memory location in one of the second locations where data is to be transferred from the first location,
(b) during the second phase of the clock cycles putting data to be transferred to the selected address location of the second location defined in step 4a on the bus, and
(c) during the third phase of the clock cycles transferring data placed on the bus during the second clock phase into the selected address location of the second location defined in step 4a;
and
(5) transferring data to and from the second locations and communicating external devices during at least some of the second clock phases;
whereby the transfer of data to and from the first and second locations is independent of the transfer of data to and from the second locations and external devices.

10 more elements

A computer comprising:

(A) a central processing unit (CPU) for the processing of data, the CPU having a processor;
(B) means, connected to the CPU for providing a communication path to and from the CPU;
(C) a composite, intelligent memory and input/output module (MIO) connected to the communication path means, so as to store and transfer data to and from the CPU and to and from external devices, the data including all application code for execution by the CPU as well as all data used in the execution of the application code, the MIO comprising:
(1) a public memory for the storage of data accessible to both the CPU and the external devices during different periods of time,
(2) a microprocessor to control public memory access by the CPU and the external devices during the different periods of time,
(3) a microprocessor bus connecting the public memory to the microprocessor,
(4) means, responsive to the microprocessor and connected to the microprocessor bus, for interfacing data to and from the external devices with the public memory, and
(2) means, responsive to the microprocessor and connected between the public memory and communication path means, for interfacing data to and from the public memory and the CPU;
whereby data transfer to and from the public memory of the MIO to the communication path means occurs during different periods of time than the transfer of data to and from the public memory of the MIO with the external devices.

6 more elements

Dependencies are inferred from the claim text.

Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same

Life of this patent

Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same

Life of this patent

Abstract

Claims36