G06F 12/0897
With two or more cache hierarchy levels
Official title: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
G06F12/0897 (With two or more cache hierarchy levels) appears on 2,270 US grants and 2,198 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,270
- Published applications
- 2,198
- Assignees
- 354
- Inventors
- 3,596
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 2 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 2 | 0 |
| 1989 | 2 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 4 | 0 |
| 1993 | 9 | 0 |
| 1994 | 7 | 0 |
| 1995 | 9 | 0 |
| 1996 | 15 | 0 |
| 1997 | 21 | 0 |
| 1998 | 46 | 0 |
| 1999 | 22 | 0 |
| 2000 | 36 | 0 |
| 2001 | 25 | 9 |
| 2002 | 48 | 21 |
| 2003 | 33 | 29 |
| 2004 | 32 | 31 |
| 2005 | 30 | 35 |
| 2006 | 31 | 57 |
| 2007 | 33 | 48 |
| 2008 | 50 | 73 |
| 2009 | 36 | 58 |
| 2010 | 48 | 49 |
| 2011 | 41 | 41 |
| 2012 | 55 | 76 |
| 2013 | 48 | 83 |
| 2014 | 70 | 92 |
| 2015 | 92 | 91 |
| 2016 | 120 | 135 |
| 2017 | 115 | 136 |
| 2018 | 137 | 153 |
| 2019 | 155 | 170 |
| 2020 | 160 | 185 |
| 2021 | 162 | 134 |
| 2022 | 147 | 130 |
| 2023 | 141 | 108 |
| 2024 | 129 | 110 |
| 2025 | 95 | 94 |
| 2026 | 55 | 50 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System and method for handling cache updates6 Oct 2026US 12,754,847 B2Ampere Computing LLC
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Canceling prefetch of cache blocks based on an address and a bit field29 Sep 2026US 12,748,591 B2SiFive, Inc.
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Cache structure and utilization15 Sep 2026US 12,737,318 B2Intel Corporation
- Inserting null vectors into a stream of vectors8 Oct 2026US 2026/0310466 A1Texas Instruments Incorporated
- Cache system and method for processing cache1 Oct 2026US 2026/0299950 A1Fujitsu Limited
- Scan and useless prefetch resistant cache controller circuit for a hardware processor1 Oct 2026US 2026/0300186 A1Intel Corporation
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Embedded memory for glass core packages1 Oct 2026US 2026/0305429 A1Intel Foundry IP LLC
Most cited
By later US patents
- Computing in parallel processing environments463US 8,738,860 B1Tilera Corporation · 2014
- Multi-tier caching system400US 6,732,237 B1Oracle International Corporation · 2004
- Method and structure for implementing a cache memory using a DRAM array337US 5,829,026 AMonolithic System Technology, Inc. · 1998
- Reducing metadata in a write-anywhere storage system331US 9,116,819 B2DataDirect Networks, Inc. · 2015
- Efficient use of hybrid media in cache architectures316US 8,397,016 B2Violin Memory, Inc. · 2013