Scan and useless prefetch resistant cache controller circuit for a hardware processor

A method comprising:

• issuing, by an execution circuit, a memory access request for a cache line of a memory;
• searching, by a cache controller circuit, a cache for the cache line;
• and
• in response to a miss in the cache for the cache line:
• causing a fill of the cache line into a way of a plurality of ways of a set of the cache, and
• setting an age for the cache line in the cache to an age less than a most recently used (MRU) age in response to the memory access request being a first type of request of a plurality of types of requests.

A system comprising:

• a system memory;
• a hardware processor core comprising a cache coupled to the system memory, and an execution circuit to issue a memory access request for a cache line;
• and
• a cache controller circuit to search the cache for the cache line, and, for a miss:
• cause a fill of the cache line from the system memory into a way of a plurality of ways of a set of the cache, and
• set an age for the cache line in the cache to an age less than a most recently used (MRU) age in response to the memory access request being a first type of request of a plurality of types of requests.