Method and structure for implementing a cache memory using a DRAM array

A computer system comprising:

• a central processing unit (CPU);
• a first level cache memory integrated with the CPU;
• a bus coupled to the CPU wherein data is transferred on the bus in response to a first clock signal having a first clock frequency, wherein data is transferred on the bus at a first data rate;
• and
• a next level cache memory coupled to the bus, wherein the next level cache memory comprises at least one dynamic random access memory (DRAM) array and a control circuit for controlling data transfer between the bus and the DRAM array, wherein the control circuit derives a second clock signal from the first clock signal, and causes data to be transferred to and from the DRAM array in response to a second clock signal at a second data rate which is faster than the first data rate, wherein the control circuit comprises a write buffer having a data output port coupled to the DRAM array and a data input port coupled to the bus, wherein the output port of the write buffer is clocked by the second clock signal and the input port of the write buffer is clocked by the first clock signal;
• wherein a first set of data values is transferred from the bus to the write buffer via the data input port and stored in the write buffer, until a second set of data values is transferred from the bus to the write buffer via the data input port, after which the first set of data values is transferred to the DRAM array via the data output port.

A method of using a DRAM array as a next level cache memory from a bus, the method comprising:

• transferring data on the bus in response to a first clock signal having a first clock frequency, wherein data is transferred on the bus at a first data rate;
• generating a second clock signal in response to the first clock signal;
• operating the DRAM array in response to the second clock signal, wherein data is transferred to and from the DRAM array at a second data rate, the second data rate being greater than the first data rate;
• reading a plurality of data values from the DRAM array to a plurality of sense amplifiers;
• reading the data values from the sense amplifiers to a read buffer memory using the second clock signal to clock the data values into the buffer memory;
• reading the data values from the read buffer memory to the bus using the first clock signal to clock the data values out of the read buffer memory so that the data values are read to the read buffer memory faster than the data values are read from the read buffer memory;
• and
• precharging bit lines of the DRAM array during the time that the data values are read from the read buffer memory to the bus.

A method of using a DRAM array as a next level cache memory from a bus, the method comprising:

• transferring data on the bus in response to a first clock signal having a first clock frequency, wherein data is transferred on the bus at a first data rate;
• generating a second clock signal in response to the first clock signal;
• operating the DRAM array in response to the second clock signal, wherein data is transferred to and from the DRAM array at a second data rate, the second data rate being greater than the first data rate;
• writing a first set of data values from the bus into a write buffer using the first clock signal to clock the first set of data values into the write buffer;
• writing a second set of data values from the bus into the write buffer using the first clock signal to clock the second set of data values into the write buffer;
• writing the first set of data values to the DRAM array after the time the second set of data values are written into the write buffer;
• and
• precharging bit lines of the DRAM array during the time the second set of data values are written into the write buffer.

A computer system comprising:

• a central processing unit (CPU);
• a first level cache memory integrated with the CPU;
• a bus coupled to the CPU wherein data is transferred on the bus in response to a first clock signal having a first clock frequency, wherein data is transferred on the bus at a first data rate;
• and
• a next level cache memory coupled to the bus, wherein the next level cache memory comprises at least one dynamic random access memory (DRAM) array and a control circuit for controlling data transfer between the bus and the DRAM array, wherein the control circuit derives a second clock signal from the first clock signal, and causes data to be transferred to and from the DRAM array in response to a second clock signal at a second data rate which is faster than the first data rate, the control circuit comprising a phase locked loop (PLL) circuit coupled to the bus, wherein the PLL circuit generates the second clock signal in response to the first clock signal, and wherein the second clock signal has the same frequency as the first clock signal.

A computer system comprising:

• a central processing unit (CPU);
• a first level cache memory integrated with the CPU;
• a bus coupled to the CPU wherein data is transferred on the bus in response to a first clock signal having a first clock frequency, wherein data is transferred on the bus at a first data rate;
• and
• a next level cache memory coupled to the bus, wherein the next level cache memory comprises at least one dynamic random access memory (DRAM) array and a control circuit for controlling data transfer between the bus and the DRAM array, wherein the control circuit derives a second clock signal from the first clock signal, and causes data to be transferred to and from the DRAM array in response to a second clock signal at a second data rate which is faster than the first data rate,
• wherein the control circuit comprises a burst sequencer which accesses the DRAM array in an asynchronous, self-timed manner with respect to the first clock signal;
• wherein the burst sequencer further comprises:
• a sense amplifier circuit coupled to the DRAM array;
• a data amplifier circuit having a plurality of data amplifiers and
• a column selector coupled between the sense amplifier circuit and the data amplifier circuit, wherein the column selector can be selected to isolate the sense amplifier circuit from the data amplifier circuit;
• wherein the burst sequencer further comprises:
• a first delay circuit coupled to the sense amplifier circuit, wherein the first delay circuit enables the sense amplifier circuit in an asynchronous manner when the data values are available from the DRAM array;
• and
• a second delay circuit coupled to the column selector, wherein the second delay circuit enables the column selector in an asynchronous manner when the data values are available in the send amplifier circuit.