G06F 12/0859
With reload from main memory
Official title: {with reload from main memory}
G06F12/0859 (With reload from main memory) appears on 360 US grants and 231 published applications in this corpus.
Search patents in G06F- Granted patents
- 360
- Published applications
- 231
- Assignees
- 100
- Inventors
- 767
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 4 | 0 |
| 1981 | 1 | 0 |
| 1982 | 3 | 0 |
| 1983 | 1 | 0 |
| 1984 | 3 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 1 | 0 |
| 1988 | 7 | 0 |
| 1989 | 2 | 0 |
| 1990 | 3 | 0 |
| 1991 | 3 | 0 |
| 1992 | 3 | 0 |
| 1993 | 2 | 0 |
| 1994 | 7 | 0 |
| 1995 | 11 | 0 |
| 1996 | 13 | 0 |
| 1997 | 10 | 0 |
| 1998 | 21 | 0 |
| 1999 | 9 | 0 |
| 2000 | 15 | 0 |
| 2001 | 16 | 1 |
| 2002 | 23 | 10 |
| 2003 | 7 | 15 |
| 2004 | 8 | 10 |
| 2005 | 12 | 12 |
| 2006 | 11 | 17 |
| 2007 | 8 | 9 |
| 2008 | 11 | 14 |
| 2009 | 10 | 15 |
| 2010 | 11 | 14 |
| 2011 | 4 | 10 |
| 2012 | 15 | 5 |
| 2013 | 7 | 5 |
| 2014 | 5 | 7 |
| 2015 | 6 | 8 |
| 2016 | 8 | 4 |
| 2017 | 4 | 4 |
| 2018 | 8 | 6 |
| 2019 | 6 | 9 |
| 2020 | 6 | 10 |
| 2021 | 9 | 5 |
| 2022 | 12 | 11 |
| 2023 | 7 | 13 |
| 2024 | 12 | 7 |
| 2025 | 5 | 4 |
| 2026 | 5 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Multi-cache based digital output generation6 Oct 2026US 12,754,843 B2Aux Mode Inc.
- Cache memory supporting data operations with parametrized latency and throughput12 May 2026US 12,625,808 B2Microsoft Technology Licensing, LLC
- Graphics processor memory access architecture with address sorting12 May 2026US 12,625,814 B2Intel Corporation
- Memory controller reservation of resources for cache hit5 May 2026US 12,619,558 B2Apple Inc.
- Apparatus and method for selecting dynamic latency for level 2 cache10 Mar 2026US 12,572,480 B2Condor Computing Corporation
- Cache memory supporting data operations with parametrized latency and throughput6 Aug 2026US 2026/0228130 A1Microsoft Technology Licensing, LLC
- Response latency in generative models2 Jul 2026US 2026/0187368 A1Google Inc.
- Apparatus and Method for Selecting Dynamic Latency for Level 2 Cache25 Jun 2026US 2026/0178511 A1Condor Computing Corporation
- Multi-cache based digital output generation11 Jun 2026US 2026/0161563 A1Aux Mode Inc.
- Cache, cache management method and electronic device4 Jun 2026US 2026/0154202 A1VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Most cited
By later US patents
- DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word229US 5,822,606 A1998
- Memory module with selectable byte addressing for digital data processing system160US 4,045,781 ADigital Equipment Corporation · 1977
- Apparatus and method for handling multiple mergeable misses in a non-blocking cache150US 6,145,054 ASun Microsystems, Inc. · 2000
- Dynamic voltage control method and apparatus141US 6,889,331 B2Analog Devices, Inc. · 2005
- Method and apparatus for processing multiple cache misses using reload folding and store merging132US 5,809,530 AMotorola, Inc. · 1998