G06F 12/0855
Overlapped cache accessing
Official title: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
G06F12/0855 (Overlapped cache accessing) appears on 1,205 US grants and 1,001 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,205
- Published applications
- 1,001
- Assignees
- 239
- Inventors
- 2,166
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 2 | 0 |
| 1980 | 6 | 0 |
| 1981 | 1 | 0 |
| 1982 | 5 | 0 |
| 1983 | 4 | 0 |
| 1984 | 4 | 0 |
| 1985 | 3 | 0 |
| 1986 | 4 | 0 |
| 1987 | 2 | 0 |
| 1988 | 10 | 0 |
| 1989 | 6 | 0 |
| 1990 | 6 | 0 |
| 1991 | 6 | 0 |
| 1992 | 7 | 0 |
| 1993 | 5 | 0 |
| 1994 | 11 | 0 |
| 1995 | 16 | 0 |
| 1996 | 24 | 0 |
| 1997 | 17 | 0 |
| 1998 | 35 | 0 |
| 1999 | 16 | 0 |
| 2000 | 26 | 0 |
| 2001 | 30 | 6 |
| 2002 | 36 | 26 |
| 2003 | 21 | 23 |
| 2004 | 19 | 18 |
| 2005 | 19 | 19 |
| 2006 | 16 | 29 |
| 2007 | 15 | 18 |
| 2008 | 16 | 25 |
| 2009 | 17 | 30 |
| 2010 | 21 | 31 |
| 2011 | 14 | 37 |
| 2012 | 35 | 14 |
| 2013 | 36 | 23 |
| 2014 | 35 | 31 |
| 2015 | 35 | 45 |
| 2016 | 37 | 33 |
| 2017 | 34 | 30 |
| 2018 | 42 | 31 |
| 2019 | 38 | 41 |
| 2020 | 43 | 103 |
| 2021 | 65 | 49 |
| 2022 | 71 | 62 |
| 2023 | 70 | 89 |
| 2024 | 95 | 87 |
| 2025 | 82 | 63 |
| 2026 | 45 | 38 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Multi-cache based digital output generation6 Oct 2026US 12,754,843 B2Aux Mode Inc.
- Systems and methods for coupled cache management25 Aug 2026US 12,717,725 B1Appian Corporation
- Allocation control for cache18 Aug 2026US 12,711,071 B2Advanced Micro Devices, Inc.
- Global coherence operations4 Aug 2026US 12,699,589 B2Texas Instruments Incorporated
- Pseudo-random way selection7 Jul 2026US 12,675,312 B2Texas Instruments Incorporated
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Methods and apparatus to facilitate read-modify-write support in a victim cache17 Sep 2026US 2026/0277825 A1
- Merging data for write allocate10 Sep 2026US 2026/0267679 A1
- Pipeline arbitration3 Sep 2026US 2026/0259764 A1
- Load store bank aware thread scheduling techniques27 Aug 2026US 2026/0252384 A1Intel Corporation
Most cited
By later US patents
- DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word229US 5,822,606 A1998
- Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer215US 5,721,855 AIntel Corporation · 1998
- Low-overhead operating systems177US 8,327,187 B1Tilera Corporation · 2012
- Memory module with selectable byte addressing for digital data processing system160US 4,045,781 ADigital Equipment Corporation · 1977
- Apparatus and method for handling multiple mergeable misses in a non-blocking cache150US 6,145,054 ASun Microsystems, Inc. · 2000