Apparatus and method for handling multiple mergeable misses in a non-blocking cache

A cache memory system comprising:

• a first non-blocking cache receiving access requests from a plurality of functional units in a processor;
• a first miss queue storing entries corresponding to access requests not serviced by said first non-blocking cache, said first miss queue having an indicator associable with each of said entries in said first miss queue, said indicator indicating whether said entry is a primary reference to data located at the address associated with said entry;
• a second non-blocking cache adapted to receive access requests from said first miss queue and from said functional unit;
• and
• a second miss queue storing entries corresponding to access requests not serviced by said second non-blocking cache, said second miss queue having an indicator associable with each of said entries in said second miss queue, said indicator indicating whether said entry is a primary reference to data located at the address associated with said entry.

A processor that executes coded instuctions comprising:

• an instruction scheduling unit receiving the coded instructions and issuing received instructions for execution;
• an instruction execution unit generating access requests in response to the issued instructions;
• a first non-blocking cache receiving access requests from said instruction execution unit;
• a first miss queue storing entries corresponding to access requests not serviced by said first non-blocking cache, said first miss queue having an indicator associable with each of said entries in said first miss queue, said indicator indicating whether said entry is a primary reference to data located at the address associated with said entry;
• a second non-blocking cache adapted to receive access requests from said first miss;
• and
• a second miss queue storing entries corresponding to access requests not serviced by said second non-blocking cache, said second miss queue having an indicator associable with each of said entries in said second miss queue, said indicator indicating whether said entry is a primary reference to data located at the address associated with said entry.