Memory controller reservation of resources for cache hit

A method, comprising:

• receiving, at a memory controller circuit of a computer system with one or more co-packaged integrated circuits (ICs), a memory access request, wherein the memory controller circuit includes a memory cache circuit;
• attempting to reserve, by the memory controller circuit, entries in a first set of a plurality of storage circuits within the memory controller circuit that are needed to process a cache hit in the memory cache circuit, without attempting to reserve other ones of the plurality of storage circuits that would be needed to be reserved in response to the memory access request generating a snoop or a cache miss, wherein the first set of storage circuits includes a retry queue circuit configured to store information for memory access requests that are determined, during a given pass through the memory controller circuit, to require another pass through the memory controller circuit;
• in response to successfully reserving entries in the first set of storage circuits, initiating, by the memory controller circuit, the memory access request;
• and
• determining, by the memory controller circuit, whether the memory access request results in a cache hit in the memory cache circuit;
• and
• wherein the other ones of the plurality of storage circuits include a different set of storage circuits used to process a cache miss, and wherein the control circuitry is configured to reserve entries in the different set of storage circuits after initiation of the memory access request and in response to a determination of the cache miss.

An apparatus, comprising:

• a computer system that includes, on one or more co-packaged integrated circuits (ICs):
• a plurality of memory plane controller circuits, wherein a given one of the plurality of memory plane controller circuits includes:
• a memory cache circuit;
• a plurality of storage circuits;
• and
• control circuitry configured to:
• receive a memory access request from a network of the computer system;
• attempt to reserve a first set of resources in the plurality of storage circuits that are needed to complete a cache hit, without attempting to reserve other sets of resources needed in case of a cache miss or a snoop, the first set of resources including an entry in a retry queue circuit that is configured to store information for memory access requests that are determined, during a given pass through the given memory plane controller circuit, to require another pass through the given memory plane controller circuit;
• initiate processing of the memory access request based on successfully reserving the first set of resources;
• inhibit processing of the memory access request based on not successfully reserving at least one of the first set of resources;
• and
• in response to detecting a cache hit for the memory access request, complete the memory access request and release a reservation for the retry queue circuit
• wherein the other sets of resources of the plurality of storage circuits include a different set of storage circuits used to process a cache miss, and wherein the control circuitry is configured to reserve entries in the different set of storage circuits after initiation of the memory access request and in response to a determination of the cache miss.

An apparatus, comprising:

• a memory controller circuit of a computer system that includes, on one or more co-packaged integrated circuits (ICs):
• a memory cache circuit;
• a plurality of storage circuits;
• and
• control circuitry configured to manage access to the memory cache circuit and a portion of a system memory by reserving ones of the plurality of storage circuits, wherein the control circuitry, in response to receiving a memory access request, is configured to attempt to reserve, prior to a determination of whether the memory access request hits in the memory cache circuit, entries in a first set of the plurality of storage circuits that are needed to process a cache hit, without reserving entries in other sets of storage circuits of the plurality of storage circuits that are needed to process other possible outcomes of the memory access request, including a cache miss;
• and
• wherein the control circuitry is configured to initiate processing of the memory access request based on successfully reserving entries in all of the first set of storage circuits, and to inhibit processing of the memory access request based on being unable to reserve an entry in at least one of the first set of storage circuits;
• and
• wherein the other sets of storage circuits of the plurality of storage circuits include a second set of storage circuits that includes a snoop queue circuit configured to store information relating to snoops generated by memory access requests, and wherein the control circuitry is configured to reserve entries in the second set of storage circuits after determining that a particular snoop has been generated for a particular memory access request.