Method and apparatus for processing multiple cache misses using reload folding and store merging

A method for efficiently processing multiple cache misses in a data processing system having an upper-level cache and a lower-level memory system comprising the steps of:

• generating a completed store request;
• determining whether a cache line associated with a data element of said completed store request is stored in the upper-level cache and if said cache line is not stored in the upper-level cache performing the steps of:
• requesting said cache line from the lower-level memory system;
• putting said completed store request into an inactive state and while in said inactive state continuing to store said data element;
• detecting when the upper-level cache receives said cache line from the lower-level memory system;
• and
• merging said data element into said cache line and subsequently storing said cache line in the upper-level cache if said cache line corresponds to said completed store request.

A data processor which efficiently processes multiple cache misses, comprising:

• an upper-level cache;
• a lower-level memory system;
• a load/store unit coupled to said upper-level cache and to said lower-level memory system for generating load/store requests, presenting said load/store requests to said upper-level cache, and presenting cache line fill requests to said lower-level memory system;
• said load/store unit including a completed store queue having a plurality of entries each of which includes an address and a data element, wherein said load/store unit presents to said upper-level cache a store request corresponding to each active entry in order;
• if said store request hits in said upper-level cache, said load/store unit storing said data element in said upper-level cache and thereafter removing said store request from said completed store queue;
• if said store request misses in said upper-level cache, said load/store unit requesting a cache line associated with said store request from said lower-level memory system and thereafter placing said store request into an inactive state;
• and
• the data processor further comparing a reload address to said address of said store request when said store request is in said inactive state and merging said data element with said cache line if said reload address matches said address of said store request.

A data processor which efficiently processes multiple cache misses, comprising:

• a upper-level cache;
• a lower-level memory system;
• a miss queue coupled to said lower-level memory system having a plurality of entries each representing an address of a corresponding load miss, said miss queue presenting to said lower-level memory system a cache line fill request corresponding to each active entry in order;
• a load/store unit coupled to said upper-level cache and to said miss queue, for generating load/store requests and for either, loading a data element of a load request from said upper-level cache if an address of said load request is present in said upper-level cache, or requesting a cache line associated with said data element from said lower-level memory system and thereafter placing said load request into an inactive state;
• said miss queue comparing a reload address of a cache line received by said upper-level cache to said address of each entry and if said address of an entry matches said reload address, said miss queue provides a critical data indication corresponding to said entry to said upper-level cache;
• and
• said upper-level cache forwarding a critical data element as determined by said critical data indication to at least one destination of the data processor before storing said cache line therein.