Dynamic voltage control method and apparatus
AssigneeAnalog Devices, Inc.
InventorsJoern Soerensen, Michael Allen, Palle Birk
Life of this patent
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AssigneeAnalog Devices, Inc.
InventorsJoern Soerensen, Michael Allen, Palle Birk
Estimating the term…
A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.
In a system including at least one processor having at least one clock signal capable of operating at a plurality of frequencies, a method of dynamic power control comprising acts of:
A processor including at least one clock signal operating at a plurality of frequencies, the processor comprising:
A controller to dynamically control the power to a processor having a plurality of clock signals, the controller comprising:
A device comprising:
Dependencies are inferred from the claim text.
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Debugging of software: by tracing the execution of the program
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
Term ended 23 Apr 2023 (estimated)
This invention relates to reducing the power consumption in processors and, more particularly, to methods and apparatus for dynamically controlling the voltage level supplied to a processor based on the processing state and/or computational demands of the processor by determining the clock frequency requirement and a corresponding voltage requirement of the processor.
Power consumption and management is a design concern for developers of processors, digital devices, computer systems etc. In battery powered devices such as cellular phones, laptop computers, person digital assistants (PDAs), and other portable and handheld devices, power consumption may be a significant contributor to the length of time during which a device may operate before the device must either be recharged and/or connected to an alternate power source. As such, power consumption may significantly impact the utility of these devices.
In some computer systems and/or digital devices, power control may provide a binary power state wherein the first power state corresponds to an idle processor and the second power state corresponds to an active processor. However, the processor in a digital device, for example, may have a variety of active processing states with computational demands that require varying levels of power to support the processing state.
FIG. 1 illustrates a block diagram various subsystems of an exemplary processor;
FIG. 2 illustrates a clocking scheme and control to generate and distribute clock signals to the various components of the processor illustrated in FIG. 1;
FIG. 3 illustrates a diagram of how exemplary clock signals of a processor may vary as a function of time in different operating modes;
In many devices, particularly battery powered devices, it is advantageous to reduce the amount of time in which the device's processor is consuming excess power. A processor is considered to be consuming excess power when the computational tasks, functions, and operations of the processor may be performed, and/or the processing demands met, at a lower power state. The term “processor” refers, generally, to any apparatus that performs logic operations, computational tasks, control functions, etc. A processor may include one or more subsystems, components, and/or other processors. A processor will typically include various logic components that operate using a clock signal to latch data, advance and/or sequence logic states, synchronize computations and logic operations, and/or provide other timing functions.
Applicant has observed that the power consumption of a device is related to the square of the voltage supplied to the device's processor and proportional to the frequency at which the processor operates. The power consumption of a device may be expressed as: PD=cV2F (Equation 1) where, V=the voltage supplied to the device (i.e., the difference between Vdd and Gnd) F=the frequency (e.g., the clock frequency of a device) c=a constant determined by the circuits operating at V and F.
In addition, Applicant has recognized that the voltage needed to operate the processor may be a function of the clock frequency or frequencies being provided and distributed to the processor. Accordingly, one way to reduce the power consumption of a device is to dynamically adjust the frequency of the clock signals provided to a processor to reflect the clock frequency requirement of the processor.