Graphics processor memory access architecture with address sorting

A method comprising:

• receiving a memory access request at circuitry of a graphics processor, wherein the circuitry is configured to perform memory load and store operations and the memory access request is received from a processing resource of the graphics processor;
• storing the memory access request to a memory access request buffer within the circuitry;
• retrieving a set of multiple memory access requests from the memory access request buffer;
• sorting the set of multiple memory access requests into an address-sorted list of memory access requests without regard to receipt order of the set of multiple memory access requests;
• storing read requests in the address-sorted list of memory access requests to a read request buffer within the circuitry;
• storing write requests in the address-sorted list of memory access requests to a write request buffer within the circuitry, the write request buffer distinct from the read request buffer;
• and
• alternately scheduling batches of multiple requests from the read request buffer and the write request buffer to reduce a memory switching penalty occurrence.

A data processing system comprising:

• a memory device;
• and
• one or more processors coupled with the memory device, the one or more processors to execute instructions stored on the memory device, the instructions to cause the one or more processors to:
• store received memory access messages to a memory access request buffer;
• sort memory access messages in the memory access request buffer to generate an address-sorted list of memory access messages;
• write one or more memory read requests to a read request buffer in response to a first memory access message in the address-sorted list of memory access messages;
• write one or more memory write requests to a write request buffer in response to a second memory access message in the address-sorted list of memory access messages, the write request buffer distinct from the read request buffer;
• via circuitry configured to process memory access messages triggered in response to instructions executed by the one or more processors:
• schedule multiple address-sorted read requests from a read request buffer during a first period of clock cycles without regard to receipt order of the memory access messages associated with the multiple address-sorted read requests;
• and
• schedule multiple address-sorted write requests from the write request buffer during a second period of clock cycles without regard to receipt order of the memory access messages associated with the multiple address-sorted write requests, the circuitry to alternately schedule batches of multiple requests from the read request buffer and the write request buffer to reduce a memory switching penalty occurrence.