G06F 12/0607
Interleaved addressing
Official title: {Interleaved addressing}
G06F12/0607 (Interleaved addressing) appears on 973 US grants and 892 published applications in this corpus.
Search patents in G06F- Granted patents
- 973
- Published applications
- 892
- Assignees
- 271
- Inventors
- 1,827
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 2 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 4 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 6 | 0 |
| 1989 | 4 | 0 |
| 1990 | 5 | 0 |
| 1991 | 3 | 0 |
| 1992 | 5 | 0 |
| 1993 | 6 | 0 |
| 1994 | 13 | 0 |
| 1995 | 6 | 0 |
| 1996 | 14 | 0 |
| 1997 | 11 | 0 |
| 1998 | 21 | 0 |
| 1999 | 7 | 0 |
| 2000 | 19 | 0 |
| 2001 | 12 | 1 |
| 2002 | 20 | 12 |
| 2003 | 16 | 19 |
| 2004 | 10 | 18 |
| 2005 | 14 | 15 |
| 2006 | 14 | 17 |
| 2007 | 14 | 13 |
| 2008 | 11 | 29 |
| 2009 | 10 | 22 |
| 2010 | 23 | 37 |
| 2011 | 21 | 27 |
| 2012 | 27 | 26 |
| 2013 | 23 | 42 |
| 2014 | 48 | 36 |
| 2015 | 41 | 45 |
| 2016 | 49 | 31 |
| 2017 | 35 | 46 |
| 2018 | 37 | 38 |
| 2019 | 50 | 51 |
| 2020 | 54 | 62 |
| 2021 | 54 | 63 |
| 2022 | 64 | 68 |
| 2023 | 56 | 56 |
| 2024 | 56 | 50 |
| 2025 | 59 | 41 |
| 2026 | 23 | 27 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Cache structure and utilization15 Sep 2026US 12,737,318 B2Intel Corporation
- Modulo operations for interleaved memory having non-power-of-two channels25 Aug 2026US 12,717,708 B2Arteris, Inc.
- Process-in-memory (PIM)-aware address hashing25 Aug 2026US 12,717,726 B2QUALCOMM Incorporated
- Method of flexible address mapping for utilizing processing-in-memory and apparatus therefor1 Oct 2026US 2026/0300168 A1Seoul National University R&Db Foundation
- System and method for sharing a cache line between non-contiguous memory areas24 Sep 2026US 2026/0288636 A1Next Silicon Ltd
- Workload mapping to matrix multiplication engines20 Aug 2026US 2026/0244569 A1OpenAl Opco, LLC
- Process-in-memory (pim)-aware address hashing20 Aug 2026US 2026/0244577 A1QUALCOMM Incorporated
- Modulo operations for interleaved memory having non-power-of-two channels6 Aug 2026US 2026/0228121 A1Arteris, Inc.
Most cited
By later US patents
- Memory addressing controlled by PTE fields435US 7,805,587 B1NVIDIA Corporation · 2010
- Synchronous interface for a nonvolatile memory331US 6,564,285 B1Intel Corporation · 2003
- Picture end token in a system comprising a plurality of pipeline stages243US 5,956,519 ADiscovision Associates · 1999
- Flash memory including a mode register for indicating synchronous or asynchronous mode of operation239US 6,026,465 AIntel Corporation · 2000
- Phantom resource memory address mapping system214US 6,185,654 B2Compaq Computer Corporation · 2001