Process-in-memory (PIM)-aware address hashing

A method of operation of a memory controller, the method comprising:

• sending, to a memory device, a first request associated with a first physical address of the memory device, wherein the first physical address is in accordance with a first address selection scheme that includes an address hashing scheme;
• and
• sending, to the memory device, a second request associated with a second physical address of the memory device, wherein, in accordance with the second request being associated with process-in-memory (PIM) operations by the memory device, the second physical address is in accordance with a second address selection scheme different than the first address selection scheme.

A non-transitory computer-readable medium storing instructions executable by one or more processors to perform operations, the operations comprising:

• sending, to a memory device, a first request associated with a first physical address of the memory device, wherein the first physical address is in accordance with a first address selection scheme that includes an address hashing scheme;
• and
• sending, to the memory device, a second request associated with a second physical address of the memory device, wherein, in accordance with the second request being associated with process-in-memory (PIM) operations by the memory device, the second physical address is in accordance with a second address selection scheme different than the first address selection scheme.