US 7,805,587 B1 · Memory addressing controlled by PTE fields

Abstract

Embodiments of the present invention enable virtual-to-physical memory address translation using optimized bank and partition interleave patterns to improve memory bandwidth by distributing data accesses over multiple banks and multiple partitions. Each virtual page has a corresponding page table entry that specifies the physical address of the virtual page in linear physical address space. The page table entry also includes a data kind field that is used to guide and optimize the mapping process from the linear physical address space to the DRAM physical address space, which is used to directly access one or more DRAM. The DRAM physical address space includes a row, bank and column address. The data kind field is also used to optimize the starting partition number and partition interleave pattern that defines the organization of the selected physical page of memory within the DRAM memory system.

Claims20

Dependent claims

A method for translating a virtual address to a physical address in a computing device, the method comprising:

searching a page table for a page table entry that corresponds to the virtual address of a two-dimensional (2D) surface that is being accessed in a local memory;
retrieving the physical address and a related set of data kind bits from the page table entry, wherein the data kind bits encode characteristics of data stored in the local memory at a transformed physical address and are used to convert the physical address into the transformed physical address;
and
computing the transformed physical address based on the physical address and the data kind bits, wherein the data kind bits encode a modification to the physical address to produce a first page bank interleave pattern for a first virtual memory page allocated to the 2D surface and a second page bank interleave pattern for a second virtual memory page allocated to the 2D surface.

1 more element

A computing device configured to translate a virtual address to a physical address, the computing device comprising:

a system memory;
and
a processing unit coupled to a local memory and including a memory controller for managing accesses to the local memory, wherein the memory controller includes a virtual-to-physical address mapping unit configured to:
search a page table for a page table entry that corresponds to the virtual address of a two-dimensional (2D) surface that is being accessed in the local memory;
retrieve the physical address and a related set of data kind bits from the page table entry, wherein the data kind bits encode characteristics of data stored in the local memory at a transformed physical address and are used to convert the physical address into the transformed physical address;
and
compute the transformed physical address based on the physical address and the data kind bits, wherein the data kind bits encode a modification to the physical address to produce a first page bank interleave pattern for a first virtual memory page allocated to the 2D surface and a second page bank interleave pattern for a second virtual memory page allocated to the 2D surface.

4 more elements

Dependencies are inferred from the claim text.

Memory addressing controlled by PTE fields

Life of this patent

Memory addressing controlled by PTE fields

Life of this patent

Abstract

Claims20