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US 2026/0288636 A1Published application
System and method for sharing a cache line between non-contiguous memory areas
AssigneeNext Silicon Ltd
InventorsDan SHECHTER, Elad RAZ
Life of this patent
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AssigneeNext Silicon Ltd
InventorsDan SHECHTER, Elad RAZ
Estimating the term…
A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.
A system for memory management, comprising at least one hardware processor adapted for encoding, in a page table entry (PTE) in a page table used by a memory management unit, a page bump indicator (PBI) indicative of an amount of contiguous physical memory pages referenced by the PTE, wherein the PBI is encoded in one or more bits of a binary representation of a virtual address in the PTE, such that the PBI is carried untranslated into a respective entry in a translation lookaside buffer (TLB) corresponding with the PTE;
A method for memory management, comprising encoding, in a page table entry (PTE) in a page table used by a memory management unit, a page bump indicator (PBI) indicative of an amount of contiguous physical memory pages referenced by the PTE, wherein the PBI is encoded in one or more bits of a binary representation of a virtual address in the PTE, such that the PBI is carried untranslated into a respective entry in a translation lookaside buffer (TLB) corresponding with the PTE;
Dependencies are inferred from the claim text.