Flash memory including a mode register for indicating synchronous or asynchronous mode of operation

A computer system comprising:

• a processor for initiating a burst read for a range of memory defined by a start address and a plurality of subsequent consecutive addresses;
• a burst logic circuit for generating consecutive addresses of a burst read sequence;
• a synchronous main emory bus coupled to the processor and the burst logic circuit, the synchronous main memory bus providing address signals and synchronous control signals including a clock signal and an address latch enable signal;
• a nonvolatile memory apparatus coupled to the burst logic circuit, comprising:
• a first bank of nonvolatile memory;
• a second bank of nonvolatile memory, wherein consecutive addresses of the nonvolatile memory apparatus are interlaced between the first and second banks;
• interlace control logic capable of receiving address signals, asynchronous control signals, and synchronous control signals including a clock signal;
• a mode register, wherein the interface control logic provides synchronous access to the first and second memor banks in accordance with the address signals and synchronous control signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing a first value, wherein the interface control logic provides asynchronous access to the first and second memor banks independent of the clock signal in accordance with the address signals and asynchronous control signals if the mode register is storing a second value;
• and
• a data multiplexer coupled to the first and second banks of nonvolatile memory, wherein the data multiplexer synchronously selects data from one of the first and second banks in accordance with the synchronous control signals and at least one bit of the address signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing the first value.