Modulo operations for interleaved memory having non-power-of-two channels
AssigneeArteris, Inc.
InventorsHao Luan, Brian Huang
Life of this patent
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Abstract
An electronic system includes system memory having N interleaved channels, where N is not a power of two. A hardware-implemented method for the electronic system includes receiving a request to access the system memory, the request including an M-bit address; and processing the address to calculate a modulo N of the address without performing division-by-N. The modulo N of the address is calculated as [Σi αi mod N*2bi mod N]mod N, where Σi αi*2bi represents the M-bit address, ai is an ith word in the address, and 2bi is a power of two associated with the ith word. The method further includes using the modulo N of the address as an offset to determine which of the N interleaved channels to access.
Claims20
A hardware-implemented method for an electronic system including system memory having N interleaved channels, where N is not a power of two, the method comprising:
- receiving a request to access the system memory, the request including an M-bit address;
- processing the address to calculate a modulo N of the address without performing division-by-N, wherein the modulo N of the address is calculated as [Σi αi mod N*2bi mod N]mod N, where Σi αi*2bi represents the M-bit address, ai is an ith word in the address, and 2bi is a power of two associated with the ith word;
- and
- using the modulo N of the address as an offset to determine which of the N interleaved channels to access.
An electronic system comprising:
- system memory having N interleaved channels, where N is not a power of two;
- and
- an address decoder configured to receive a request to access the system memory, the request including an M-bit address;
- process the address to calculate a modulo N of the address without performing division-by-N, wherein the modulo N of the address is calculated as [Σi αi mod N*2bi mod N]mod N, where Σi αi*2bi represents the M-bit address, ai is an ith word in the address, and 2bi is a power of two associated with the ith word;
- and
- adjust the address with the modulo N to ensure divisibility by N and provide the modulo N of the address as an offset to determine which of the N interleaved channels to access.
A network-on-chip comprising:
- a transport interconnect;
- a target network interface unit (NIU) configured for an interleaved N-channel system memory, where N is not a power of two;
- and
- a plurality of initiator NIUs for communicating with the target NIU via the transport interconnect;
- wherein at least one of the network interface units includes an address decoder configured to decode an M-bit address, including:
- processing the address to calculate a modulo N of the address without performing division-by-N, wherein the modulo N of the address is calculated as [Σi αi mod N*2bi mod N]mod N, where Z, ai*2bi represents the M-bit address, ai is an ith word in the address, and 2bi is a power of two associated with the ith word;
- and
- adjusting the address with the modulo N to ensure divisibility by N and providing the modulo N as an offset to determine which interleaved N-channels to access.
Dependencies are inferred from the claim text.