G06F 11/1064
In cache or content addressable memories
Official title: {in cache or content addressable memories}
G06F11/1064 (In cache or content addressable memories) appears on 688 US grants and 624 published applications in this corpus.
Search patents in G06F- Granted patents
- 688
- Published applications
- 624
- Assignees
- 160
- Inventors
- 1,259
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 2 | 0 |
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 4 | 0 |
| 1989 | 4 | 0 |
| 1990 | 4 | 0 |
| 1991 | 3 | 0 |
| 1992 | 0 | 0 |
| 1993 | 3 | 0 |
| 1994 | 4 | 0 |
| 1995 | 3 | 0 |
| 1996 | 7 | 0 |
| 1997 | 6 | 0 |
| 1998 | 6 | 0 |
| 1999 | 9 | 0 |
| 2000 | 8 | 0 |
| 2001 | 4 | 1 |
| 2002 | 4 | 8 |
| 2003 | 9 | 10 |
| 2004 | 11 | 22 |
| 2005 | 12 | 10 |
| 2006 | 17 | 11 |
| 2007 | 18 | 25 |
| 2008 | 16 | 19 |
| 2009 | 11 | 19 |
| 2010 | 29 | 17 |
| 2011 | 12 | 21 |
| 2012 | 23 | 49 |
| 2013 | 35 | 32 |
| 2014 | 41 | 31 |
| 2015 | 35 | 30 |
| 2016 | 44 | 40 |
| 2017 | 32 | 30 |
| 2018 | 29 | 17 |
| 2019 | 33 | 26 |
| 2020 | 31 | 43 |
| 2021 | 29 | 25 |
| 2022 | 29 | 25 |
| 2023 | 33 | 28 |
| 2024 | 37 | 31 |
| 2025 | 29 | 34 |
| 2026 | 16 | 20 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Caching for object stores22 Sep 2026US 12,743,357 B1Qumulo, Inc.
- Hardware pipeline for cache coherent interconnect including snoop filters18 Aug 2026US 12,711,070 B2Arteris, Inc.
- Streaming engine with cache-like stream data storage and lifetime tracking14 Jul 2026US 12,681,726 B2Texas Instruments Incorporated
- Adaptive parity techniques for a memory device30 Jun 2026US 12,670,065 B2Micron Technology, Inc.
- Methods and apparatus for eviction in dual datapath victim cache system16 Jun 2026US 12,657,134 B2Texas Instruments Incorporated
- Handling parity data during data folding in a memory device8 Oct 2026US 2026/0310550 A1
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Methods and apparatus to facilitate read-modify-write support in a victim cache17 Sep 2026US 2026/0277825 A1
- Input/output memory management unit-based data integrity control27 Aug 2026US 2026/0252440 A1International Business Machines Corporation
- Hardware pipeline for cache coherent interconnect including snoop filters16 Jul 2026US 2026/0203223 A1Arteris, Inc.
Most cited
By later US patents
- Method and apparatus for recovering from correctable ECC errors189US 5,912,906 ASun Microsystems, Inc. · 1999
- Non-volatile random access memory in computer primary memory187US 9,250,999 B1Google Inc. · 2016
- Memory module with selectable byte addressing for digital data processing system160US 4,045,781 ADigital Equipment Corporation · 1977
- NAND power fail recovery116US 7,941,692 B2Intel Corporation · 2011
- TLB tag parity checking without CAM read107US 7,366,829 B1Sun Microsystems, Inc. · 2008