Method and apparatus for recovering from correctable ECC errors

An integrated system comprising:

• a first memory cache on a chip;
• a second memory cache on said chip;
• a third memory cache, wherein data is stored in said third cache from a memory external to said chip;
• a first bus for providing said data to said first cache from said third cache;
• a second bus for providing said data to said second cache from said third cache;
• and
• a first ECC circuit, coupled to said second bus, wherein said first ECC circuit checks for errors in said data on said second bus;
• wherein said data is provided to said first cache without being checked for errors, such that said data is provided to said first cache at least one clock cycle before said data is provided to said second cache.

A method of providing data to a first cache and a second cache in an integrated system from a third cache, the method comprising the steps of:

• a) providing data to the first cache from the third cache over a first bus in response to an instruction;
• b) providing said data to a first ECC circuit from the third cache over a second bus in response to said instruction;
• c) checking said data for errors in said first ECC circuit;
• and thereafter
• d) providing said data to the second cache from said first ECC circuit over said second bus, such that said data is provided to said first cache at least one clock cycle before said data is provided to said second cache.