Adaptive parity techniques for a memory device
AssigneeMicron Technology, Inc.
InventorsJustin Eno, William A. Melton, Sean S. Eilert
Life of this patent
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Abstract
Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.
Claims20
A memory device, comprising:
- one or more memory arrays;
- a cache comprising a plurality of entries indicating addresses of the one or more memory arrays;
- and
- one or more controllers coupled with the one or more memory arrays and the cache, and configured to cause the memory device to:
- receive a command to read data from the one or more memory arrays, the command indicating an address associated with the data;
- determine, based at least in part on receiving the command, whether the cache includes an entry indicating the address;
- read the data from the one or more memory arrays;
- and
- perform one or more error control processes on the data based at least in part on determining whether the cache includes the entry.
A memory device, comprising:
- one or more memory arrays;
- a cache comprising a plurality of entries indicating addresses of the one or more memory arrays;
- and
- one or more controllers coupled with the one or more memory arrays and the cache, and configured to cause the memory device to:
- receive a command to write data to the one or more memory arrays, the command indicating an address associated with the data;
- determine, based at least in part on receiving the command, whether the cache includes an entry indicating the address;
- perform one or more error control processes based at least in part on determining whether the cache includes the entry;
- and
- write the data to the one or more memory arrays based at least in part on performing the one or more error control processes.
A memory device, comprising:
- one or more memory arrays configured to store data;
- a cache comprising a plurality of entries associated with the data;
- and
- one or more controllers coupled with the one or more memory arrays and the cache, and configured to cause the memory device to:
- perform one or more error control processes using the cache;
- identify no errors are present in first data read from the one or more memory arrays based at least in part on performing the one or more error control processes;
- and
- remove, from the cache, one or more entries associated with the first data based at least in part on identifying no errors are present in the first data.
Dependencies are inferred from the claim text.