TLB tag parity checking without CAM read
AssigneeSun Microsystems, Inc.
InventorsMark A. Luttrell, Paul J. Jordan
Life of this patent
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Abstract
An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag parity value in a RAM portion of a TLB, using the CAM key input to generate a tag parity check value for a matched entry, and comparing the generated tag parity check value to the stored tag parity value to determine if there is a parity match or error.
Claims17
A single chip multithreaded processor comprising:
- at least one processor core that generates memory requests using a first addressing scheme;
- a cache memory coupled to said processor core for servicing the memory requests using a second addressing scheme;
- a translation lookaside buffer for translating the first addressing scheme to the second addressing scheme by performing a lookup operation using an input key value to generate an output value, said translation lookaside buffer comprising at least a first entry formed of a tag entry portion stored in a CAM and a data entry portion stored in a RAM, where said data entry portion in the RAM contains a stored tag parity value that is generated based on at least part of the tag entry portion, and where said translation lookaside buffer supports a plurality of types of address translation, and where the data entry portion stored in the RAM contains a stored tag parity value corresponding to the type of address translation of the translation lookaside buffer entry, and where the parity checking unit generates tag parity check values for each type of address translation and selects from among the generated tag parity check values to output the tag parity check value;
- and
- a parity checking unit for receiving a first input key value that has matched with the tag entry portion stored in the CAM, generating a first tag parity check value based on at least part of the first input key value, and comparing the first tag parity check value with the stored tag parity value corresponding to the matched tag entry portion to determine if there is a parity error in the matched tag entry portion, during access to the translation lookaside buffer.
A translation buffer containing a plurality of translation entries for translating a first protocol to a second protocol, comprising:
- a CAM array for storing a tag portion of each entry in the translation buffer;
- a data array for storing a data portion of each entry in the translation buffer, said data portion including a stored tag parity value that is generated from at least part of the tag portion of said entry;
- and
- means for parity checking a tag portion of an entry in the translation buffer by comparing the stored tag parity value from the data portion of a matched entry with a generated tag parity value that is generated from at least part of a key value that is input to the CAM array, during access to the translation buffer, without accessing the CAM array, wherein the parity checking means includes:
- means for calculating a plurality of tag parity values, each calculated tag parity value being calculated based on a unique subset of the key value that is input to the CAM array;
- and
- means for selecting between the plurality of calculated tag parity values to output the generated tag parity value.
In an integrated circuit buffer for holding a plurality of entries comprising a CAM array for storing a tag portion of each entry and a data array for storing a corresponding data portion of each entry, a method for parity checking the tag portion of each entry, during access to the integrated circuit buffer, without accessing the CAM array, comprising:
- receiving an input key value that has matched with a tag entry portion stored in the CAM;
- retrieving a stored tag parity value from the data portion corresponding to the matched tag entry portion;
- calculating a generated tag parity value based on at least part of the input key value, wherein calculating the generated tag further includes;
- calculating a plurality of tag parity values, each calculated tag parity value being calculated based on a different subset of the input key value;
- and
- selecting between the plurality of calculated tag parity values to output the generated tag parity value in response to an indicator contained in the input key value;
- and
- comparing the generated tag parity value with the stored tag parity value to determine if there is a parity error in the matched tag portion, during access to the integrated circuit buffer.
Dependencies are inferred from the claim text.