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US 9,250,999 B1Granted
Non-volatile random access memory in computer primary memory
AssigneeGoogle Inc.
InventorLuiz Andre Barroso
Life of this patent
Estimating the term…
Abstract
A method includes deploying non-volatile random access memory (NVRAM) in a memory arrangement coupled to a CPU core of a computing device via a memory bus. The method further includes configuring the CPU core to conduct NVRAM read operations directly over the memory bus, and providing an I/O logic device to process write instructions initiated by the CPU core as a Direct Memory Access (DMA) write operation on the NVRAM.
Claims25
A method comprising:
- providing non-volatile random access memory (NVRAM) in a primary memory of a computing device, the primary memory including dynamic random access memory (DRAM), the primary memory coupled to a central processing unit (CPU) core of a computing device via a memory bus, the CPU core configured to conduct NVRAM read operations directly over the memory bus;
- and
- using an input/output (I/O) logic device coupled to the CPU core to process a write instruction initiated by the CPU core as a Direct Memory Access (DMA) write operation on the NVRAM, the I/O logic device coupled to the CPU core as a peripheral device to the computing device via an I/O bus.
A computing device comprising:
- a processor including one or more central processing units (CPUs), the CPUs coupled to a primary memory of the computing device disposed on a memory bus, the primary memory including dynamic random-access memory (DRAM), the CPUs coupled to the primary memory via the memory bus and a memory controller;
- a non-volatile random access memory (NVRAM) disposed in the primary memory;
- and
- a NVRAM write controller connected to the CPUs and the primary memory, the NVRAM write controller configured to access the primary memory independently of the one or more CPUs,
- wherein the processor is configured to conduct NVRAM read operations initiated by the one or more CPUs through the memory controller and to conduct NVRAM write operations initiated by the one or more CPUs through the NVRAM write controller configured to access the primary memory independently of the one or more CPUs.
2 more elements
Dependencies are inferred from the claim text.