Wave Computing, Inc.
Santa Clara, CA, US· latest recorded location
Wave Computing, Inc. is named on 27 US grants and 48 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 27
- Published applications
- 48
- Inventors
- 26
- Granted in 2026 so far
- 0
- Most recent grant
- 18 Jan 2022
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2016 | 1 | 2 |
| 2017 | 4 | 6 |
| 2018 | 4 | 10 |
| 2019 | 9 | 20 |
| 2020 | 5 | 5 |
| 2021 | 3 | 1 |
| 2022 | 1 | 2 |
| 2023 | 0 | 0 |
| 2024 | 0 | 2 |
By publication year.
Technology areas
Share of 75 documents
- G06FComputing and data processing60
- G06NAI and machine learning29
- H03KPulse technique14
- H04LDigital communication5
- G11CStatic stores2
- Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information2
- G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial1
- H04WWireless communication networks1
Recent patents
- Matrix multiplication engine using pipelining18 Jan 2022US 11,227,030 B2
- Neural network output layer for machine learning31 Aug 2021US 11,106,976 B2
- Multidimensional address generation for direct memory access4 May 2021US 10,997,102 B2
- Data flow graph computation using exceptions16 Mar 2021US 10,949,328 B2
- Reconfigurable fabric direct memory access with multiple read or write elements21 Jul 2020US 10,719,470 B2
- Processor Cluster Address Generation27 Jun 2024US 2024/0211397 A1
- Processor graph execution using interrupt conservation22 Feb 2024US 2024/0061704 A1
- Integer matrix multiplication engine using pipelining17 Nov 2022US 2022/0366010 A1
- Processor graph execution using interrupt conservation23 Jun 2022US 2022/0197692 A1
- Processor cluster address generation14 Jan 2021US 2021/0011849 A1
Most cited
By later US patents
- Logical elements with switchable connections7US 9,590,629 B22017
- Compact logic evaluation gates using null convention7US 9,692,419 B22017
- Data transfer circuitry given multiple source elements4US 10,374,981 B12019
- Multi-threshold flash NCL logic circuitry with flash reset4US 9,385,715 B22016
- Extensible iterative multiplier4US 9,563,401 B22017