Integer matrix multiplication engine using pipelining

A processor-implemented method comprising:

• obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;
• distilling the first integer matrix and the second integer matrix into (j×j) submatrices;
• configuring dynamically both a variable radix point format and an initial value for an accumulator register;
• executing multiply-accumulate (MAC) operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result;
• and
• using the executed MAC operations to process data in a data-flow architecture.

One or more non-transitory computer readable media embodying one or more instructions that are operable when executing by one or more processors to perform operations of:

• obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;
• distilling the first integer matrix and the second integer matrix into (j×j) submatrices;
• configuring dynamically both a variable radix point format and an initial value for an accumulator register;
• executing multiply-accumulate operations in a pipelined architecture—on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result;
• and
• using the executed MAC operations to process data in a data-flow architecture.

A system comprising:

• a memory which stores instructions;
• and one or more processors coupled to the memory wherein the one or more processors, when executing the instructions, are configured to:
• obtain a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;
• distill the first integer matrix and the second integer matrix into (j×j) submatrices;
• configure dynamically both a variable radix point format and an initial value for an accumulator register;
• and
• execute multiply-accumulate operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result;
• and
• use the executed MAC operations to process data in a data-flow architecture.