Matrix multiplication engine using pipelining

A computer program product embodied in a non-transitory computer readable medium for data manipulation, the computer program product comprising code which causes one or more processors to perform operations of:

• obtaining a first matrix with dimensions m×k and a second matrix with dimensions k×n for matrix multiplication within a processor;
• configuring a first matrix multiply-accumulate (MAC) unit within the processor, wherein the first MAC unit accepts input elements of the first matrix and the second matrix, and wherein a first element of the first matrix and a first element of the second matrix are presented to the first MAC unit on a first cycle;
• configuring a second MAC unit within the processor in pipelined fashion, wherein the second MAC unit accepts input elements of the first matrix and the second matrix, wherein the first element of the first matrix and a second element of the second matrix are presented to the second MAC unit on a second cycle, and wherein a second element of the first matrix and the first element of the second matrix are presented to the first MAC unit on the second cycle;
• further configuring one or more additional MAC units within the processor in pipelined fashion;
• and
• executing multiply-accumulate operations in pipelined fashion.

A computer system for data manipulation comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• obtain a first matrix with dimensions m×k and a second matrix with dimensions k×n for matrix multiplication within a processor;
• configure a first matrix multiply-accumulate (MAC) unit within the processor, wherein the first MAC unit accepts input elements of the first matrix and the second matrix, and wherein a first element of the first matrix and a first element of the second matrix are presented to the first MAC unit on a first cycle;
• configure a second MAC unit within the processor in pipelined fashion, wherein the second MAC unit accepts input elements of the first matrix and the second matrix, wherein the first element of the first matrix and a second element of the second matrix are presented to the second MAC unit on a second cycle, and wherein a second element of the first matrix and the first element of the second matrix are presented to the first MAC unit on the second cycle;
• further configure one or more additional MAC units within the processor in pipelined fashion;
• and
• execute multiply-accumulate operations in pipelined fashion.