Extensible iterative multiplier
AssigneeWave Computing, Inc.
InventorsSamit Chaudhuri, Radoslav Danilak
Life of this patent
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Abstract
An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands.
Claims20
An apparatus for mathematical manipulation comprising:
- a first multiplier logic which can multiply two binary numbers of a first width;
- a second multiplier logic which can multiply two binary numbers of a second width;
- and
- a connection between the first multiplier logic and the second multiplier logic that enables multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.
A method of logical calculation comprising:
- configuring a first multiplier logic which can multiply two binary numbers of a first width and a second multiplier logic which can multiply two binary numbers of a second width through a connection between the first multiplier logic and the second multiplier logic to enable multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.
A computer implemented method for implementation of a logical calculation apparatus comprising:
- implementing a first multiplier logic which can multiply two binary numbers of a first width;
- implementing a second multiplier logic which can multiply two binary numbers of a second width;
- and
- implementing a connection between the first multiplier logic and the second multiplier logic that enables multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.
A computer program product embodied in a non-transitory computer readable medium for implementation of a logical calculation apparatus comprising code which causes one or more processors to perform operations of:
- implementing a first multiplier logic which can multiply two binary numbers of a first width;
- implementing a second multiplier logic which can multiply two binary numbers of a second width;
- and
- implementing a connection between the first multiplier logic and the second multiplier logic that enables multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.
A computer system for implementation of a logical calculation apparatus comprising:
- a memory which stores instructions;
- one or more processors coupled to the memory wherein the one or more processors are configured to:
- implement a first multiplier logic which can multiply two binary numbers of a first width;
- implement a second multiplier logic which can multiply two binary numbers of a second width;
- and
- implement a connection between the first multiplier logic and the second multiplier logic that enables multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.
Dependencies are inferred from the claim text.