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US 9,385,715 B2Granted
Multi-threshold flash NCL logic circuitry with flash reset
AssigneeWave Computing, Inc.
InventorGajendra Prasad Singh
Life of this patent
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Abstract
Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.
Claims17
A logic circuit comprising:
- a gate comprised of a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
- a plurality of input lines, each having an asserted state and a null state, connected to the gate;
- a flash input line, having a first state and a second state, connected to the gate;
- an output line, having an asserted output state and a null output state, connected to the gate;
- a high-threshold transistor in a pull-up path of the plurality of transistors that provide for logical evaluation that is used to reset the gate and set the output line into the null output state;
- a second high-threshold transistor wherein the second high-threshold transistor is in a pull-up path for an output inverter and is gated based on the flash input line to the gate;
- and
- a third high-threshold transistor wherein the third high-threshold transistor is in a pulldown path of the output inverter.
5 more elements
A computer-implemented method for using logical evaluation comprising:
- forming a logic gate from of a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
- including a plurality of input lines, each having an asserted state and a null state, connected to the gate;
- providing a flash input line, having a first state and a second state, connected to the gate;
- observing an output line, having an asserted output state and a null output state, connected to the gate;
- including a high-threshold transistor in a pull-up path of the plurality of transistors that provide for logical evaluation that is used to reset the gate and set the output line into the null output state;
- including a second high-threshold transistor wherein the second high-threshold transistor is in a pull-up path for an output inverter and is gated based on the flash input line to the gate;
- and
- including a third high-threshold transistor wherein the third high-threshold transistor is in a pulldown path of the output inverter.
5 more elements
An m-of-n flash-type threshold gate comprising:
- a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
- a plurality of n input lines, each having an asserted state and a null state, connected to the gate;
- a flash input line, having a first state and a second state, connected to the gate;
- an output line, having an asserted output state and a null output state, connected to the gate wherein the output line transitions to the asserted output state when m of the n input lines are in their respective asserted states;
- a high-threshold transistor in a pull-up path of the plurality of transistors that provide for logical evaluation that is used to reset the gate and set the output line into the null output state;
- a second high-threshold transistor wherein the second high-threshold transistor is in a pull-up path for an output inverter, coupled to the output line, and is gated based on the flash input line to the gate;
- and
- a third high-threshold transistor wherein the third high-threshold transistor is in a pulldown path of the output inverter.
5 more elements
Dependencies are inferred from the claim text.