Multidimensional address generation for direct memory access

A computer program product embodied in a non-transitory computer readable medium for data manipulation, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing one or more processor clusters capable of executing software-initiated work requests;
• configuring a direct memory access (DMA) engine coupled to the one or more processor clusters, wherein the DMA engine employs address generation across a plurality of tensor dimensions;
• parsing a work request address field, wherein the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor;
• generating DMA addresses, based on the unique address space descriptors and the common address space descriptor;
• and
• accessing memory, using two or more of the DMA addresses that were generated, wherein the two or more DMA addresses enable processing within the one or more processor clusters.

A computer system for data manipulation comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access one or more processor clusters capable of executing software-initiated work requests;
• configure a direct memory access (DMA) engine coupled to the one or more processor clusters, wherein the DMA engine employs address generation across a plurality of tensor dimensions;
• parse a work request address field, wherein the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor;
• generate DMA addresses, based on the unique address space descriptors and the common address space descriptor;
• and
• access memory, using two or more of the DMA addresses that were generated, wherein the two or more DMA addresses enable processing within the one or more processor clusters.