Compact logic evaluation gates using null convention

A computer-implemented method for using a logic implementation comprising:

• obtaining a pair of inputs where the pair of inputs comprises a null convention logic true input and a null convention logic complement input, wherein the null convention logic true input and the null convention logic complement input have values of “0, 0”to indicate a null condition;
• applying the null convention logic true input to a null convention logic true input of a null convention logic gate;
• applying the null convention logic complement input to a null convention logic complement input of the null convention logic gate;
• evaluating outputs for the null convention logic gate based on the null convention logic true input and the null convention logic complement input, wherein the evaluated outputs retain a value based on a last previous non-null value applied to the pair of inputs;
• and
• propagating a completion signal, wherein the completion signal is based on the pair of inputs and the evaluated outputs for the null convention logic gate.

A computer-implemented method for logic implementation comprising:

• designing a plurality of transistors to form a logic gate wherein:
• the logic gate includes a pair of inputs where the pair of inputs comprises a null convention logic true input and a null convention logic complement input, wherein the null convention logic true input and the null convention logic complement input have values of “0, 0”to indicate a null condition;
• the logic gate is coupled to the pair of inputs wherein:
• the plurality of transistors provides for logical signal capture;
• the plurality of transistors includes a pair of cross-coupled inverters;
• the plurality of transistors includes a first pull-down device with a transistor-gate node coupled to the null convention logic true input;
• the plurality of transistors includes a second pull-down device with a transistor-gate node coupled to the null convention logic complement input;
• a “1”on the null convention logic true input causes a first side of the pair of cross-coupled inverters to go to a “0”state;
• a “1”on the null convention logic complement input causes a second side of the pair of cross-coupled inverters to go to a “0”state;
• and
• the plurality of transistors includes a completion circuit, coupled to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters, wherein the completion circuit is responsive to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters.

A computer system for logic implementation comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors are configured to:
• design a plurality of transistors to form a logic gate wherein:
• the logic gate includes a pair of inputs where the pair of inputs comprises a null convention logic true input and a null convention logic complement input, wherein the null convention logic true input and the null convention logic complement input have values of “0, 0”to indicate a null condition;
• the logic gate is coupled to the pair of inputs wherein:
• the plurality of transistors provides for logical signal capture;
• the plurality of transistors includes a pair of cross-coupled inverters;
• the plurality of transistors includes a first pull-down device with a transistor-gate node coupled to the null convention logic true input;
• the plurality of transistors includes a second pull-down device with a transistor-gate node coupled to the null convention logic complement input;
• a “1”on the null convention logic true input causes a first side of the pair of cross-coupled inverters to go to a “0”state;
• a “1”on the null convention logic complement input causes a second side of the pair of cross-coupled inverters to go to a “0”state;
• and
• the plurality of transistors includes a completion circuit, coupled to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters, wherein the completion circuit is responsive to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters.