Upmem
GRENOBLE, FR· latest recorded location
UPMEM is named on 8 US grants and 12 published applications in this corpus. Its most frequent classification is G11C (Static stores).
- Granted patents
- 8
- Published applications
- 12
- Inventors
- 5
- Granted in 2026 so far
- 0
- Most recent grant
- 26 Aug 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2018 | 0 | 2 |
| 2019 | 1 | 1 |
| 2020 | 1 | 0 |
| 2021 | 3 | 3 |
| 2022 | 2 | 0 |
| 2023 | 0 | 1 |
| 2024 | 0 | 3 |
| 2025 | 1 | 2 |
By publication year.
Technology areas
Share of 20 documents
Recent patents
- Memory device provided with dram memory circuits arranged in such a way as to minimize the size of a memory block allowing management of the row-hammering26 Aug 2025US 12,400,700 B2
- Methods and devices for bypassing the internal cache of an advanced DRAM memory controller8 Nov 2022US 11,494,308 B2
- Method and circuit for protecting a DRAM memory device from the row hammer effect14 Jun 2022US 11,361,811 B2
- Row hammer correction logic for dram with integrated processor29 Jun 2021US 11,049,544 B2
- Computing device within memory processing and narrow data ports5 Jan 2021US 10,884,657 B2
- Memory device provided with dram memory circuits arranged in such a way as to minimize the size of a memory block allowing management of the row-hammering effect18 Sep 2025US 2025/0292820 A1
- Dram memory device using a mechanism for row hammer management17 Apr 2025US 2025/0124965 A1
- Memory device provided with dram memory circuits arranged in such a way as to minimize the size of a memory block allowing management of the row-hammering11 Jul 2024US 2024/0233800 A9
- Memory device and method for protecting a memory device from the effect of row hammering6 Jun 2024US 2024/0185910 A1
- Memory device provided with dram memory circuits arranged in such a way as to minimize the size of a memory block allowing management of the row-hammering25 Apr 2024US 2024/0135981 A1
Most cited
By later US patents
- Method and circuit for protecting a DRAM memory device from the row hammer effect10US 10,885,966 B12021
- Row hammer correction logic for dram with integrated processor10US 11,049,544 B22021
- Computing device within memory processing and narrow data ports2US 10,884,657 B22021
- Method and circuit for protecting a DRAM memory device from the row hammer effect2US 11,361,811 B22022