Row hammer correction logic for dram with integrated processor
AssigneeUpmem
InventorsFabrice Devaux, Gilles Hamou
Life of this patent
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AssigneeUpmem
InventorsFabrice Devaux, Gilles Hamou
Estimating the term…
A memory device comprises one or more bank(s), each bank comprising a plurality of DRAM memory rows, the memory device further comprising: an external access port configured to allow an external memory controller to activate and then access the memory rows of each bank; one or more internal processor(s) capable of activating and then accessing the memory rows of each bank; a logic for detecting triggering of the Row Hammer configured to monitor, for each bank, the activation commands from the external memory controller and from one or more internal processor(s), the logic for detecting triggering including memory storage and a logic for sending preventive refresh configured to implement a refresh operation for one or more of the adjacent rows of each identified row by emitting refresh requests instead of the periodic refresh requests generated by the external memory controller, delaying one or more of said periodic refresh requests.
A memory device comprising one or more banks, each bank comprising several rows of DRAM memory, the memory device further comprising:
A method for protecting a memory device from the Row Hammer effect, the memory device comprising one or more bank(s), each bank comprising a plurality of DRAM memory rows, the method comprising the steps of:
Dependencies are inferred from the claim text.